Method for fabricating MOS transistors having gates with different work functions

• US 4,745,079 A
• Filed: 03/30/1987
• Issued: 05/17/1988
• Est. Priority Date: 03/30/1987
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Pfiester, James R.
• Primary Examiner(s): Roy, Upendra
• Application Number:
  US07/031,299
• Time in Patent Office: 414 Days
• Field of Search: 437/29, 437/46, 437/45, 437/157, 357/23.14, 357/23.5
• US Class Current: 438/306
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 21/32155 Doping polycristalline - or amorphous silicon layers
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: Y10S 148/082 Ion implantation FETs/COMs

Abstract

A method for fabricating an insulated gate field effect transistor (IGFET) having a semiconductor gate with a first portion and a second portion where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon gate of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. A semiconductor material layer, such as polycrystalline silicon (polysilicon) is selectively protected by a gate pattern mask whereby the end portions of the gates are produced by the lateral diffusion of the dopant under the edges of the gate pattern mask. Thus, the technique for defining the different portions of the gate uses other than photolithographic techniques which are limited in their resolution capabilities, and thus is readily implementable in submicron device feature processes.

Claims

1. A method for fabricating an insulated gate field effect transistor (IGFET) comprising the steps of:

providing a semiconductor substrate;

forming a layer of gate dielectric material on the semiconductor substrate;

forming a layer of semiconductor material on the gate dielectric material layer;

providing a pattern of masking material on the layer of semiconductor material, through which selected areas of the layer of semiconductor material are exposed;

introducing an impurity of a first conductivity type into the selected areas of the semiconductor material layer;

diffusing the impurity of the first conductivity type a selected distance into the semiconductor material layer laterally under the masking material pattern, wherein the selected distance is less than that required to completely dope the semiconductor material under the masking material pattern, leaving a central portion of the conductive material pattern undoped with the impurity of the first conductivity type; and

providing an impurity of a second conductivity type into the central portion.

2. The process of claim 1 wherein a thin layer of dielectric material is provided on top of the layer of semiconductor material before the formation of the masking material pattern.

3. The process of claim 1 wherein a thin layer of dielectric material is provided over the gate after the selected areas of the semiconductor material are removed, prior to the introduction of an impurity of a second conductivity type in the central portion of the gate and the source/drain regions.

4. The process of claim 1 wherein after the introduction of the impurity of the second conductivity type into the central portion of the gate, a strap of conductive material is provided over the end portions and the central portion of the gate to strap them together electrically.

5. The process of claim 1 wherein after the diffusion of the impurity of the first conductivity type a selected distance laterally into the semiconductor material layer, the selected areas of the semiconductor material are removed to leave a gate of semiconductor material having end portions and a central portion between the end portions, the end portions being doped with the impurity of a first conductivity type.

6. The process of claim 5 wherein after the selected areas of the semiconductor material layer are removed, an impurity of a second conductivity type is introduced into the central portion of the gate and the semiconductor substrate using the gate as mask to simultaneously form a doped central portion and doped source/drain regions respectively, of a second conductivity type.

7. The process of claim 5 wherein the pattern of masking material is removed after the selected areas of the semiconductor material are removed.

8. A method for fabricating an insulated gate field effect transistor (IGFET) comprising the steps of:

providing a semiconductor substrate lightly doped with an impurity;

forming a layer of gate dielectric material on the semiconductor substrate;

forming a layer of semiconductor material on the gate dielectric material layer;

providing a pattern of masking material on the layer of semiconductor material, through which selected areas of the layer of semiconductor material are exposed;

introducing an impurity of a first conductivity type into the selected areas of the semiconductor material layer;

diffusing the impurity of the first conductivity type in the selected areas of the semiconductor material layer a selected distance into the semiconductor material layer laterally under the masking material pattern, wherein the selected distance is less than that required to completely dope the semiconductor material under the masking layer, leaving a central portion of the conductive material pattern undoped with the impurity of the first conductivity type;

removing the selected areas of the semiconductor material to leave a gate of semiconductor material having end portions and the central portion between the end portions, the end portions being lightly doped with the impurity of the first conductivity type; and

providing an impurity of a second conductivity type in the central portion.

9. The process of claim 8 wherein a thin layer of silicon dioxide is provided on top of the layer of semiconductor material before the formation of the masking material pattern.

10. The process of claim 8 wherein a thin layer of silicon dioxide is provided over the gate after the selected areas of the semiconductor material are removed, prior to the introduction of an impurity of a second conductivity type in the central portion of the gate and the source/drain regions.

11. The process of claim 8 wherein after the introduction of the impurity of the second conductivity type into the central portion of the gate, a strap of conductive material is provided over the end portions and the central portion of the gate to strap them together electrically.

12. The method of claim 8 wherein after the selected areas of the semiconductor material layer are removed, an impurity of a second conductivity type is introduced into the central portion of the gate and the semiconductor substrate using the gate as mask to simultaneously form a heavily doped central portion and heavily doped source/drain regions respectively, of a second conductivity type.

13. The method of claim 8 wherein after the selected areas of the semiconductor material layer are removed, the pattern of masking material is removed.

14. A process for fabricating an insulated gate field effect transistor (IGFET) comprising the steps of:

providing a monocrystalline silicon substrate lightly doped with an impurity of a first conductivity type;

forming a layer of gate silicon oxide on the silicon substrate;

forming a layer of undoped polycrystalline silicon on the gate silicon oxide layer;

providing a pattern of masking material on the layer of polycrystalline silicon, through which selected areas of the layer of polycrystalline silicon are exposed;

introducing an impurity of the first conductivity type into the selected areas of the polycrystalline silicon layer;

diffusing the impurity of the first conductivity type in the selected areas of the polycrystalline silicon layer a selected distance into the polycrystalline silicon layer laterally under the masking material pattern;

removing the selected areas of the polycrystalline silicon to leave a polycrystalline silicon gate having end portions and a central portion therebetween, the end portions being lightly doped with the impurity of a first conductivity type; and

introducing an impurity of a second conductivity type into the central portion of the gate and the silicon substrate using the gate as mask to simultaneously form a heavily doped central portion and heavily doped source/drain regions respectively, of a second conductivity type.

15. The process of claim 14 wherein the polycrystalline silicon layer is doped with an impurity after it is formed and before the masking material pattern is provided.

16. The process of claim 14 wherein a thin layer of silicon dioxide is provided on top of the polycrystalline silicon layer before the formation of the masking material pattern.

17. The process of claim 14 wherein the masking material pattern is selected from the group consisting of silicon oxide, silicon nitride and a combination of silicon oxide and silicon nitride.

18. The process of claim 14 wherein a thin layer of silicon dioxide is provided over the gate after the selected areas of the polycrystalline silicon layer are removed, prior to the introduction of an impurity of a second conductivity type in the central portion of the gate and the source/drain regions.

19. The process of claim 14 wherein after the introduction of the impurity of the second conductivity type into the central portion of the gate, a strap of conductive material is provided over the end portions and the central portion of the gate to strap them together electrically.

20. The process of claim 14 wherein the strap of conductive material is selected from the group consisting of doped semiconductor material, a metal, a refractory metal silicide or a combination thereof.

21. The process of claim 14 wherein the pattern of masking material is removed after the removal of the selected area of polycrystalline silicon.