Duty cycle timer

• US 4,745,629 A
• Filed: 06/19/1987
• Issued: 05/17/1988
• Est. Priority Date: 09/26/1986
• Status: Expired due to Fees

• Current Assignee: United Technologies Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: United Technologies Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Shah, Rajendra K., Essig, Thomas W.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US07/061,600
• Time in Patent Office: 333 Days
• Field of Search: 377/20, 377/55, 377/56, 377/44, 377/107, 377/110, 377/109, 328/129.1, 328/130.1, 328/58, 328/61, 361/196, 307/265, 307/597, 307/608, 62/80, 62/155, 62/157
• US Class Current: 377/20
• CPC Class Codes: F25B 2600/23 Time delays
• CPC Class Codes: F25D 21/008 by timer
• CPC Class Codes: H03K 17/292 in thyristor, unijunction transistor or programmable unijunction transistor switches
• CPC Class Codes: H03K 17/296 Time-programme switches providing a choice of time-intervals for executing more than one switching action and automatically terminating their operation after the programme is completed electronic clocks comprising means to be operated at preselected times or after preselected time-intervals G04G15/00
• CPC Class Codes: H03K 3/03 Astable circuits

Abstract

An improved duty cycle timer provides a duty cycle control signal having alternate "on" and "off" intervals of different logic states. The timer utilizes integrated circuitry having first and second independent clock sources respectively driving first and second multistage, binary counters. One counter measures the "off" interval and the other counter measures the "on" interval. Each counter provides a signal representative of the completion of the interval which it measures, and that signal is connected to a resetting input of the opposite counter for initiating the measuring interval of that opposite counter. Typically, one interval is longer than the other. The duty cycle control signal is provided by the output of one of the counters. In an illustrated embodiment, the duty cycle timer controls operation of a defrost mechanism for a refrigeration circuit and the "off" interval is longer than the "on" interval. Associated "hold" circuitry is operative to suspend operation of the duty cycle timer when some particular demand is satisfied, but resumes operation of the timer from where it stopped when the particular demand returns.

Claims

1. An improved duty cycle timer for providing a duty cycle control signal, said duty cycle control signal having alternate "on" and "off" intervals of different logic states, said timer comprising:

integrated circuit means including first clock signal generating means for generating a first frequency clock, second clock signal generating means for generating a second frequency clock independent of said first clock, first electronic counting means responsive to said first clock for measuring a predetermined one of said "on" and "off" time intervals and providing a signal representative of the completion thereof, and second electronic counting means responsive to said second clock for measuring the other one of said "on" and "off" time intervals and providing a signal representative of the completion thereof, said first and said second clock signal generating means each being responsive to a two-state "enable or hold" signal to respectively enable or inhibit operation of the respective said clock signal generating means, any count in said first and said second counting means remaining static during application of said "hold" signal thereto;

means for connecting a two-state "enable or hold" signal to said first and second clock signal generating means and having an input terminal adapted to have an AC voltage connected thereto and disconnected therefrom and including rectifying means operatively connected to a "hold" potential and to said first and said second clock signal generating means for applying an "enabling" DC potential to said clock signal generating means when said AC voltage is connected to said input terminal and for applying said "hold" potential to said clock signal generating means when said AC voltage is disconnected from said input terminal;

circuit means, including resetting circuitry, cross-connecting said first and said second electronic counting means in complementary relation for initiating said measurement of said "on" and said "off" time intervals respectively from a reset condition of the respective one of said first and said second electronic counting means in response to said signals representative of the completion of the preceding said "off" and "on" time intervals respectively; and

wherein said duty cycle control signal is provided by at least one of said first and said second electronic counting means.

2. An improved duty cycle timer for providing a duty cycle control signal, said duty cycle control signal having alternate "on" and "off" intervals of different logic states, said timer comprising:

integrated circuit means including first clock signal generating means for generating a first frequency clock, second clock signal generating means for generating a second frequency clock independent of said first clock, first electronic counting means comprising a first multistage binary counter responsive to said first clock for measuring a predetermined one of said "on" and "off" time intervals and providing a signal representative of the completion thereof, and second electronic counting means comprising a second multistage binary counter responsive to said second clock for measuring the other one of said "on" and "off" time intervals and providing a signal representative of the completion thereof, said interval measured by said first electronic counting means being longer than said interval measured by said second electronic counting means and said signals representative of the completion of said "off" and said "on" time intervals being provided by the respective final operative stages of the respective said multistage counters;

circuit means, including resetting circuitry, cross-connecting said first and said second electronic counting means in complementary relation for initiating said measurement of said "on" and said "off" time intervals respectively from a reset condition of the respective one of said first and said second electronic counting means in response to said signals representative of the completion of the preceding said "off" and "on" time intervals respectively, each said multistage counter being reset by the application of a particular logic signal level to a respective reset input to the respective said counter, said counter being maintained in said reset condition while said particular logic signal level is maintained at said reset input, and wherein said cross-coupling of said first and second electronic counting means coupler the respective said signals representative of completion of said "off" and said "on" intervals to the respective said reset inputs of the respective said counters to thereby at least release said reset condition; and

wherein said duty cycle control signal is provided by at least one of said first and said second electronic counting means.

3. The timer of claim 2 wherein said duty cycle control signal is provided by a predetermined stage of one of said multistage counters.

4. The timer of claim 3 wherein said first clock signal generating means and said first electronic counting means are incorporated in first integrated circuit means and said second clock signal generating means and said second electronic counting means are incorporated in a second integrated circuit means separate from said first integrated circuit means.

5. The timer of claim 3 wherein said predetermined stage of said multistage counter is the final operative stage thereof.

6. The timer of claim 5 wherein said duty cycle control signal is provided by said predetermined stage of said first counting means.

7. The timer of claim 2 including signal delay means, said signal delay means being included in said circuit means which cross-connect the final stage of said first counting means to said second counting means to inhibit any race condition between said first and said second counting means.

8. An improved defrost timer for providing a defrost timing control signal, said timing control signal having alternate "ON" and "OFF" intervals of different logic states, said timer comprising:

means including first and second different RC time constants for generating respective first and second electronic clock signals at rates different from and independent of each other, said clock signal generating means being responsive to a two-state "enable or hold" control signal for respectively enabling or inhibiting generation of said first and second clock signals by said electronic clock signal generating means;

electronic counting means responsive, in alternate succession, to the first clock for a first interval and to the second clock for a second interval to provide an output signal representative of an "OFF" interval during said first interval until a first predetermined count is reached and representative of an "ON" interval during said second interval until a second predetermined count is reached, said "ON" and said "OFF" time intervals respectively being initiated by the completion of the preceding "OFF" and "ON" time intervals respectively and said defrost timing control signal being provided by said output signal of said electronic counting means; and

means for connecting a two-state "enable or hold" control signal to said clock signal generating means, so that said first and second clock signals are held frozen and any count in said electronic counting means remains static during application of said "hold" control signal to said clock signal generating means.

9. The timer of claim 8 wherein said predetermined count of said counting means is the same during each of said first and said second intervals.

10. The timer of claim 8 wherein said means for connecting a two-state "enable or hold" signal to said first and second clock signal generating means has an input terminal adapted to have an AC voltage connected thereto and disconnected therefrom and includes rectifying means operatively connected to a "hold" potential and to said first and said second clock signal generating means for applying an "enabling" DC potential to said clock signal generating means when said AC voltage is connected to said input terminal and for applying said "hold" potential to said clock signal generating means when said AC voltage is disconnected from said input terminal.

11. The timer of claim 8 wherein said electronic counting means comprises multistage binary counting means and said output signal is provided by a predetermined stage of said multistage counting means.

12. The timer of claim 11 further including switch means having a control electrode for controlling the flow of electrical current to a load device in response to said defrost timing control signal being applied to said control electrode, and means for connecting said defrost timing control signal to said control electrode.

13. The timer of claim 8 wherein at least one of said first and second RC time constants is adjustable for varying the rate of a respective one of said first and second clock signals.

14. The timer of claim 13 wherein said first RC time constant is adjustable for varying the rate of said first clock signal thereby to vary said "OFF" time interval.