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Planar tungsten interconnect

  • US 4,746,621 A
  • Filed: 12/05/1986
  • Issued: 05/24/1988
  • Est. Priority Date: 12/05/1986
  • Status: Expired due to Term
First Claim
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1. A method of forming an interconnect level for VLSI devices, comprising:

  • forming on a planar surface of a VLSI wafer a first silicon dioxide dielectric layer, said first layer having a planar top surface;

    forming a second layer of a second dielectric material on said top surface of said first layer to produce a composite dielectric;

    patterning and etching said composite dielectric to produce at least one interconnect channel in said first layer, said channel extending through said second layer, whereby said second layer forms a mask for said channel in said first layer;

    implanting silicon in the exposed bottom surface of said silicon dioxide interconnect channel through said mask;

    removing said mask;

    selectively depositing a refractory metal in said interconnect channel to fill said channel to the level of said planar top surface of said first layer to thereby form a metal interconnect line, said line and said first layer forming a first planar interconnect level.

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