Planar tungsten interconnect
First Claim
1. A method of forming an interconnect level for VLSI devices, comprising:
- forming on a planar surface of a VLSI wafer a first silicon dioxide dielectric layer, said first layer having a planar top surface;
forming a second layer of a second dielectric material on said top surface of said first layer to produce a composite dielectric;
patterning and etching said composite dielectric to produce at least one interconnect channel in said first layer, said channel extending through said second layer, whereby said second layer forms a mask for said channel in said first layer;
implanting silicon in the exposed bottom surface of said silicon dioxide interconnect channel through said mask;
removing said mask;
selectively depositing a refractory metal in said interconnect channel to fill said channel to the level of said planar top surface of said first layer to thereby form a metal interconnect line, said line and said first layer forming a first planar interconnect level.
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Accused Products
Abstract
A planar interconnect using selective deposition of a refractory metal such as tungsten into oxide channels is disclosed. A layer of silicon dioxide as thick as the desired tungsten interconnect is placed on the surface of a substrate such as an integrated circuit wafer. Thereafter, a layer of silicon nitride about 100 nm thick is formed on the silicon dioxide. Channels are formed in the silicon dioxide by patterning and etching the composite dielectric layers. After the photoresist is removed, silicon or tungsten atoms at 40 KeV are implanted in the silicon dioxide channels, the silicon nitride acting as a mask. Typically, a dosage as high as 1×1017 cm-2 is used. The silicon or tungsten implant allows seeding of the tungsten or other refractory metal. The silicon nitride mask is selectively removed by a hot phosphoric acid solution, and a metal film is then selectively deposited to fill the channels in the silicon dioxide layer, which then forms a level of interconnects. The process is repeated to form vias and subsequent levels of interconnects.
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Citations
11 Claims
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1. A method of forming an interconnect level for VLSI devices, comprising:
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forming on a planar surface of a VLSI wafer a first silicon dioxide dielectric layer, said first layer having a planar top surface; forming a second layer of a second dielectric material on said top surface of said first layer to produce a composite dielectric; patterning and etching said composite dielectric to produce at least one interconnect channel in said first layer, said channel extending through said second layer, whereby said second layer forms a mask for said channel in said first layer; implanting silicon in the exposed bottom surface of said silicon dioxide interconnect channel through said mask; removing said mask; selectively depositing a refractory metal in said interconnect channel to fill said channel to the level of said planar top surface of said first layer to thereby form a metal interconnect line, said line and said first layer forming a first planar interconnect level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification