Split bus system interface
First Claim
1. A bus system comprising:
- first and second bus halves, each half comprising a plurality of parallel lines for transmitting handshake signals, data signals and command signals;
a central processor connected to one of said bus halves for transmitting commands over said first bus half;
a plurality of communicating devices connected to said first and second bus halves for transmitting and receiving data signals and check signals;
a first interface including a parallel series converter having an input connected to said first bus half and an output;
a second interface having a series parallel converter having an input, and an output connected to an input of an elastic buffer storage means, said elastic storage means having a parallel output connected to said second bus half; and
a connection path extending between said first interface parallel/series converter output and said second interface series/parallel converter input, whereby a device connected to one bus half communicates handshake signals with an interface connected to said one bus half, and data received by said second interface is stored in said elastic store and then retransmitted over said second bus half.
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Accused Products
Abstract
A bus system, comprising a bus formed by a plurality of parallel lines for data transmission handshake signals and general management signals, the bus being coupled to a central processor and to a plurality of devices for transmitting and/or receiving data signals and checking signals. The system is in the data mode when the central processor is inoperative and the system is in the command mode when the central processor is operative. The bus is split into a left-hand bus half and a right-hand bus half, the series arrangement of a first interface circuit, a connecting path and a second interface circuit being arranged between the two bus halves, at least one of the interface circuits including a parallel-series-converter whose input is coupled to the associated bus half and whose output is coupled to the connecting path, the other interface including a series-parallel converter whose input is coupled to the connecting path and whose output is coupled to the associated bus half through an elastic data store, when the system is in the data mode, a device which wants to transmit data from one bus half to the other bus half will exchange the handshake signals with the interface circuit to which this device is connected through one bus half. A device connected to the other bus half through the connecting path will exchange the handshake signals with the interface circuit to which this device is connected through the other bus half.
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Citations
4 Claims
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1. A bus system comprising:
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first and second bus halves, each half comprising a plurality of parallel lines for transmitting handshake signals, data signals and command signals; a central processor connected to one of said bus halves for transmitting commands over said first bus half; a plurality of communicating devices connected to said first and second bus halves for transmitting and receiving data signals and check signals; a first interface including a parallel series converter having an input connected to said first bus half and an output; a second interface having a series parallel converter having an input, and an output connected to an input of an elastic buffer storage means, said elastic storage means having a parallel output connected to said second bus half; and a connection path extending between said first interface parallel/series converter output and said second interface series/parallel converter input, whereby a device connected to one bus half communicates handshake signals with an interface connected to said one bus half, and data received by said second interface is stored in said elastic store and then retransmitted over said second bus half. - View Dependent Claims (2, 3, 4)
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Specification
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- Resources
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Current AssigneeUS Philips Corporation (Koninklijke Philips N.V.)
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Original AssigneeUS Philips Corporation (Koninklijke Philips N.V.)
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InventorsDijkers, Gerardus J. P., Dieleman, Adrianus H.
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Primary Examiner(s)YUSKO, DONALD
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Application NumberUS06/940,474Time in Patent Office531 DaysField of Search340/825.06, 340/825.05, 340/825.52, 370/60, 370/94, 370/86, 370/70, 370/26, 370/83, 370/84, 370/85US Class Current370/438CPC Class CodesG06F 13/4045 where the bus bridge perfor...G06F 13/405 where the bridge performs a...G06F 13/4059 where the synchronisation u...
