Vertical depletion-mode j-MOSFET
First Claim
1. A vertical j-MOSFET transistor comprising a plurality of cells connected in parallel between a common drain electrode and a common source electrode, the cells being aligned in a two-dimensional regular array except at localized sites spaced apart in the array, and means at each such site for serving as a sink and for collecting minority charge carriers which tend to build up at each interface of a channel region and gate electrode of the transistor when a voltage is applied to the gate electrode for depleting the channel region of majority charge carriers.
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Accused Products
Abstract
A vertical j-MOSFET useful as a power transistor includes a two-dimensional array of square cells in which a small fraction of the cells are replaced by a double-junction sink useful for collecting the minority carriers in the channel regions that normally will accumulate at each interface of the gate electrode and channel region.
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Citations
9 Claims
- 1. A vertical j-MOSFET transistor comprising a plurality of cells connected in parallel between a common drain electrode and a common source electrode, the cells being aligned in a two-dimensional regular array except at localized sites spaced apart in the array, and means at each such site for serving as a sink and for collecting minority charge carriers which tend to build up at each interface of a channel region and gate electrode of the transistor when a voltage is applied to the gate electrode for depleting the channel region of majority charge carriers.
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7. A vertical j-MOSFET which comprises a semiconductor chip which includes a patterned buried insulator layer which divides the chip into a front portion and a back portion and a plurality of channel portions extending between the front and back portions through openings in the buried insulator layer, a gate electrode on said front surface and insulated therefrom, and divided into a plurality of segments for controlling the channel portions, the outer surface of the front portion including a segmented first current-carrying electrode and the outer surface of the back portion including a second current-carrying electrode, and means for collecting minority charge carriers that tend to build up at the interface of each channel portion with its segment of the gate electrode, characterized in that:
the chip is divided into a plurality of sites by the first current-carrying electrode, the patterned insulator layer, and the segmented gate electrode, the sites being arranged in a periodic two-dimensional array, a majority of the sites being occupied by cells formed by the segments of first current-carrying electrode and their associated current paths, and a minority of the sites being occupied by the means for serving as sinks. - View Dependent Claims (8, 9)
Specification