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Vertical depletion-mode j-MOSFET

  • US 4,746,960 A
  • Filed: 07/27/1987
  • Issued: 05/24/1988
  • Est. Priority Date: 07/27/1987
  • Status: Expired due to Fees
First Claim
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1. A vertical j-MOSFET transistor comprising a plurality of cells connected in parallel between a common drain electrode and a common source electrode, the cells being aligned in a two-dimensional regular array except at localized sites spaced apart in the array, and means at each such site for serving as a sink and for collecting minority charge carriers which tend to build up at each interface of a channel region and gate electrode of the transistor when a voltage is applied to the gate electrode for depleting the channel region of majority charge carriers.

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