Dual operating system computer

• US 4,747,040 A
• Filed: 10/09/1985
• Issued: 05/24/1988
• Est. Priority Date: 10/09/1985
• Status: Expired due to Term

• Current Assignee: Locus Computing Corp. (Broadcom, Inc.), NCR Corporation
• Original Assignee: American Telephone & Telegraph Company (AT&T, Inc.), AT&T Information Systems Inc. (AT&T, Inc.), Locus Computing Corp. (Broadcom, Inc.)
• Inventors: Butterfield, David A., Keverian, Kenneth M., Popek, Gerald J., Kline, Charles S., Blanset, David R.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/785,842
• Time in Patent Office: 958 Days
• Field of Search: 364/200 MS File
• US Class Current: 718/108
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

The UNIX® and MS-DOS® operating systems are supported in a multi-tasking computer. At the heart of the computer is a microprocessor having protected and non-protected modes. The computer includes special-purpose hardware which prevents the MS-DOS system and its applications, which execute in the non-protected mode, from interfering with the UNIX system and its applications, which execute in the protected mode. In particular, this hardware monitors addresses generated by the computer and, by selectively inhibiting the associated control pulses, prevents the MS-DOS system from, for example, writing in UNIX-system-allocated memory, or accessing I/O devices that the UNIX system is currently using. In addition, a context switching feature is provided whereby the user can select, via a keyboard operation, to have displayed on the computer video monitor at any given time the image generated from the current UNIX system screen data or the image generated from the current MS-DOS system screen data.

Claims

1. A digital computer capable of concurrently executing at least first and second programs, said computer comprising

a processor having a protected mode of operation and a non-protected mode of operation,

means for causing said first and second programs to be executed in said protected and non-protected modes of said processor, respectively, and

means operative prior to at least the initiation of the execution of said second program for identifying individual addressable entities in said computer to which access by said second program is to be inhibited and operative when said second program is executing for inhibiting access to said individual entities.

2. A computer of the type in which a selected one of a plurality of addressable entities connected to an address bus is accessed during a bus cycle by generating on said address bus an address associated with said addressable entity and thereafter generating a control pulse on a control lead and extending it to said selected entity, said computer comprising

a processor having a protected mode of operation and a non-protected mode of operation,

means operative when said processor is operating in said protected mode for identifying at least an individual one of said addressable entities to which access by code executing in said non-protected mode is to be limited, and

means operative when said processor is in said non-protected mode and in response to the generation on said address bus during a particular bus cycle of the address associated with said individual one of said addressable entities for inhibiting the control pulse subsequently generated on said control lead during said bus cycle.

3. A computer comprising

a bus,

a processor connected to said bus having a protected mode of operation and a non-protected mode of operation, said processor issuing on said bus instructions each identifying an entity connected to said bus to be accessed in a specified manner,

means operative when said processor is operating in said protected mode for identifying individual ones of said entities to which access is to be inhibited when said processor is thereafter operating in said non-protected mode, and

means operative when said processor is thereafter operating in said non-protected mode for precluding the completion of the execution of instructions identifying said individual ones of said entities.

4. The invention of claim 3 further comprising means connected to said bus for trapping at least said instructions identifying said individual ones of said entities and means for selectively re-issuing onto said bus ones of said trapped instructions.