Write circuit for an erasable programmable read only memory device of a microcomputer

• US 4,747,079 A
• Filed: 09/17/1986
• Issued: 05/24/1988
• Est. Priority Date: 09/17/1985
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Yamaguchi, Satoru
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/908,208
• Time in Patent Office: 615 Days
• Field of Search: 365/94, 365/103, 365/182, 365/189, 365/233
• US Class Current: 365/189.08
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

A write circuit for an EPROM device of a microcomputer comprises a first circuit responsive to an external clock signal WCLK and machine clock signals for supplying a clock signal CLK to a program counter of the microcomputer so as to successively increment an address produced in the program counter, where the external clock signal WCLK has a frequency lower than those of the machine clock signals and the clock signal CLK has different frequencies during normal and write-in operation modes so that the address produced in the program counter is successively incremented in synchronism with the machine clock signals during the normal operation mode and is successively incremented in synchronism with the external clock signal WCLK during the write operation mode, and a second circuit responsive to the machine clock signals and a bit data of a LSB of the address from the program counter for generating a bit line clock signal BCLK for inhibiting a write-in data from being written into the EPROM device during a time period in which the address changes.

Claims

1. A write circuit for an erasable programmable read only memory device of a microcomputer, said microcomputer including a program counter for providing an address and operating in synchronization with machine clock signals, said write circuit comprising:

a clock generating circuit, coupled to receive an external clock signal and the machine clock signals, for supplying a clock signal to said program counter in response to the external clock signal and the machine clock signals so as to successively increment the address produced in the program counter, the external clock signal having a frequency lower than the frequencies of the machine clock signals, the clock signal having different frequencies during a normal operation mode and a write-in operation mode so that the address produced in the program counter is successively incremented in synchronization with the machine clock signals during the normal operation mode and is successively incremented in synchronization with the external clock signal during the write operation mode; and

a bit line clock generating circuit, coupled to receive the machine clock signals and a least significant bit of the address from the program counter, for generating a bit line clock signal for inhibiting a write-in data from being written into the erasable programmable read only memory device in response to the machine clock signals and least significant bit of the address during a time period in which the address changes.

2. A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in claim 1, wherein the machine clock signals comprise first and second machine clock signals having mutually different phases so that pulses thereof do not overlap, wherein said clock generating circuit is supplied with a control signal indicating whether the operation mode of the erasable programmable read only memory device is a normal operation mode or a write-in operation mode, said clock generating circuit generating the clock signal which rises and falls in response to transitions of the first and second machine clock signals when the control signal indicates the normal operation mode, wherein the clock signal undergoes a first transition in response to a transition of the second machine clock signal and undergoes a second transition in response to a transition of the first machine clock signal only when the external clock signal undergoes a transition.

3. A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in claim 2, wherein said clock generating circuit generates the clock signal which rises with a rise in the first machine clock signal and falls with a rise the second machine clock signal when the control signal CNTL2 indicates the normal operation mode, and generates the clock signal CLK which falls with a rise in the second machine clock signal and rises with a rise in the first machine clock signal only when the external clock signal falls.

4. A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in claim 2, wherein the first and second machine clock signals have a period on the order of several microseconds, and wherein the clock signal has a period on the order of fifty milliseconds.

5. A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in claim 1, wherein the machine clock signals comprise first and second machine clock signals having mutually different phases so that pulses thereof do not overlap, and wherein said bit line clock generating circuit comprises:

a delay circuit for delaying bit data of a least significant bit of the address by using one of the first and second machine clock signals so as to produce a delayed bit data;

an exclusive-OR circuit coupled to receive the bit data and the delayed bit data of the least significant bit of the address and outputting an output signal; and

a NOR circuit coupled to receive an output signal of said exclusive-OR circuit and a control signal indicative of whether the operation mode of the erasable programmable read only memory device is the normal operation mode or the write-in operation mode, said NOR circuit producing the bit line clock signal.

6. A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in claim 1, wherein the clock signal has a period which is sufficiently long for writing information into the erasable programmable read only memory device during the write operation mode.

7. A write circuit for an erasable programmable read only memory device of a microcomputer as claimed in claim 1, further comprising:

a word line driver, coupled to receive the address from said program counter for driving a word line of said erasable programmable read only memory device; and

a bit line driver, coupled to receive write-in data and the bit line clock signal from said bit line clock generating circuit, for driving a bit line in the erasable programmable read only memory device excluding the time period in which the address changes.

8. A write circuit for an erasable programmable read only memory device coupled to receive machine clock signals, comprising:

a bit line driver circuit coupled to the erasable programmable read only memory device;

a word line driver circuit coupled to the erasable programmable read only memory device;

a program counter, coupled to said word line driver circuit, for providing a write-in address to said word line driver circuit; and

a write timing control circuit coupled to said program counter and said word line driver, including;

a clock generator circuit, coupled to said program counter and coupled to receive an external low frequency clock signal and a control signal during a write operation, for enabling said program counter to generate a write-in address in accordance with the external low frequency clock signal and the control signal; and

a bit line clock generator circuit, coupled to said program counter, said bit line driver and said word line driver, for receiving a least significant bit of the write-in address from said program counter and the control signal, and inhibiting a write-in data from being supplied to the erasable programmable read only memory device from said bit line driver circuit.

9. A write circuit as set forth in claim 8, wherein said clock generator circuit comprises:

a first transfer gate coupled to receive the external low frequency clock signal;

a second transfer gate coupled to said first transfer gate;

an AND gate coupled to said first and second transfer gates;

a NOR gate coupled to said AND gate and connected to receive the control signal; and

a gate circuit, coupled to said NOR circuit, outputting a clock signal to said program counter.

10. The write circuit as set forth in claim 8, wherein said bit line clock generator circuit comprises:

a first transfer gate coupled to receive the least significant bit of the address;

a second transfer gate coupled to said first transfer gate;

a third transfer gate coupled to said second transfer gate;

an exclusive-OR gate coupled to said third transfer gate and said first transfer gate; and

a NOR circuit, coupled to said exclusive-OR gate and coupled to receive the control signal, for providing an output signal to said bit line driver circuit.