Video display system using memory with parallel and serial access employing serial shift registers selected by column address

• US 4,747,081 A
• Filed: 12/30/1983
• Issued: 05/24/1988
• Est. Priority Date: 12/30/1983
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Novak, Mark F., Pinkham, Raymond, VanAken, Jerry R., Heilveil, Andrew, Guttag, Karl M., Redwine, Donald J.
• Primary Examiner(s): Moffitt, James W.
• Application Number:
  US06/567,110
• Time in Patent Office: 1,607 Days
• Field of Search: 365/219, 365/230, 365/240, 340/798, 340/799, 340/800
• US Class Current: 365/219
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence

Abstract

In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, column address to the RAM unit is also used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the shift register containing only the data bits of interest.

Claims

1. A memory device comprising:

an array of memory cells, said memory cells arranged in rows and columns;

address input means, for receiving row address signals and column address signals;

row decode means, for selecting a row in said array responsive to a row address signal received by said address input means;

column decode means, for selecting a column in said selected row responsive to a column address signal received by said address input means;

random input means, for writing data to said memory cell selected by said column decode means;

random output means, for presenting the contents of said memory cell selected by said column decode means;

a register comprised of a plurality of memory cells;

means for transferring the contents of the memory cells in said selected row of said array into the memory cells of said register;

serial output means, connected to a selected memory cell in said register, for presenting the contents of said selected memory cell in said register;

transfer control means, responsive to a transfer control signal, for selectively enabling and disabling said transferring means so that, when said transferring means is disabled, data may be written to and read from any of said memory cells in said array independently from the presentation of data by said serial output means;

serial selecting means for selecting a memory cell in said register to be connected to said serial output means, responsive to said address input means receiving a column address signal after said transferring means is enabled; and

means, responsive to a serial clock signal, for shifting to the serial output means the contents of another memory cell in said register so that, upon a series of said serial clock signals, the contents of a series of memory cells in said register will be presented by said serial output means;

wherein said serial selecting means comprises;

a plurality of taps, each of said taps connected to a preselected memory cell in said register;

an output circuit, connected to said serial output means; and

decode means, responsive to said address input means receiving a column address signal after said transferring means is enabled, for connecting said output circuit to the tap corresponding to said column address signal.

2. The memory device of claim 1, wherein said column address signal comprises a plurality of digital signals;

and wherein said tap corresponds to fewer than all of said plurality of digital signals comprising said column address signal.

3. The memory device of claim 1, wherein said memory cells in said register are serially connected with respect to one another;

and wherein said register is connected to said shifting means so that, responsive to said serial clock signal, the contents of each memory cell in said register is shifted to the next memory cell in said register serially connected thereto.

4. The memory device of claim 3, further comprising:

serial input means, connected to a memory cell in said register, for writing data into said memory cell connected thereto;

and wherein said transferring means also is for transferring the contents of said memory cells in said register to a like number of memory cells in said array.

5. The memory device of claim 4, wherein said serial input means writes data into said memory cell connected thereto concurrently with the presentation of data by said serial output means.

6. The memory device of claim 4, further comprising:

means for sensing the contents of the memory cells in said selected row;

wherein said transferring means, responsive to said transfer control means, transfers the sensed contents of said memory cells in said selected row to said memory cells in said register after said sensing means has sensed the contents of the memory cells in said selected row;

and further comprising;

transfer direction control means, responsive to a transfer direction signal, for controlling said transferring means so that said transferring means either transfers the contents of the memory cells in said selected row to said memory cells in said register, or transfers the contents of said memory cells in said register to said memory cells in said selected row, depending upon the transfer direction signal.