Apparatus for determining the degree of consistency of a feature in a region of an image that is divided into discrete picture elements

• US 4,747,152 A
• Filed: 05/21/1986
• Issued: 05/24/1988
• Est. Priority Date: 05/23/1985
• Status: Expired due to Term

• Current Assignee: ContextVision AB
• Original Assignee: ContextVision AB
• Inventors: Knutsson, Hans, Granlund, Gosta, Hedlund, Martin
• Primary Examiner(s): Boudreau, Leo H.
• Assistant Examiner(s): Mancuso, Joseph
• Application Number:
  US06/865,343
• Time in Patent Office: 734 Days
• Field of Search: 382/21, 382/22, 382/50, 382/51, 382/41, 382/47, 382/56
• US Class Current: 382/197
• CPC Class Codes: G06T 7/00 Image analysis
• CPC Class Codes: G06V 10/462 Salient features, e.g. scale invariant feature transforms [SIFT]

Abstract

The invention concerns an apparatus for determining the degree of consistency of a feature in a region of an image that is divided into discrete picture elements, the feature being represented by vector valued signals, one for each picture element, the vector direction describing the feature class and the vector magnitude describing the certainty in the feature assertion. The invention is characterized by a first unit (4) for weighted summation of the vectors in the region after predetermined rotations thereof, a second unit (5) for weighted summation of the magnitudes of the vectors in the region, and a norming unit (6) for norming the output signal from the first summation unit with respect to the sum of the output signal from the second summation unit and a reference signal (FIG. 2).

Claims

1. Apparatus comprising:

first means for recording a first image of a physical object or scene and dividing said first image into discrete picture elements;

second means for transforming said first image which has been divided into discrete picture elements into a vector representation, said vector representation comprising vector valued signals,

third means for accessing said vector valued signals from a plurality of picture elements which collectively form a plurality of overlapping regions of a vector valued image, one vector valued signal for each element of said plurality of picture elements, each of said vector valued signals having a vector direction which describes features class and a vector magnitude which describes certainty in feature assertion;

fourth means coupled to said accessing means for producing a first vector valued output signal for each region of said plurality of overlapping regions, said first vector valued output signal, in each respective region, being representative of vector valued signals which have been rotated a predetermined amount and then subjected to a weighted summation;

fifth means coupled to said accessing means for producing a second output signal, for each region of said plurality of overlapping regions, representative of weighted summation of said magnitude of said vector valued signals in each respective region; and

,

sixth means coupled to said fourth and fifth means for norming said first vector valued output signal, for each region of said plurality of overlapping regions, with respect to the sum of said second output signal, for each region of said plurality of overlapping regions, and a reference signal, for each region of said plurality of overlapping regions thereby producing a second image representing characterizing properties of a recorded image of said physical object or scene.

2. Apparatus according to claim 1 wherein said fourth means includes a cosine generator to a first multiplicator which is coupled to a first adder, provided with a feed back to function as a summator, which is coupled to a converter, and wherein said fourth means further includes a sine generator coupled to a second multiplicator which is coupled to a second adder, provided with a feed back to function as a summator, which is coupled to said converter, said vector direction being represented by phase signals which are provided to said cosine generator and said sine generator for conversion to cosine and sine components, respectively, said cosine component being provided to a first input of said first multiplicator, and said sine component being provided to a first input of said second multiplicator, said vector magnitude being represented by magnitude signals which are provided to a second input of said first multiplicator and a second input of said second multiplicator, the resulting product of said cosine component and said magnitude signals being provided as an input to said first adder, and the resulting product of said sine component and said magnitude signals being provided as an input to said second adder, the output of said first adder and the output of said second adder being provided to respective inputs of said converter which converts the output of said first adder and said second adder from a first and second rectangular coordinate to a first and second polar coordinate in the form of a magnitude output signal and a phase output signal.

3. Apparatus according to claim 2 wherein said fourth means includes a third multiplicator coupled to a memory, said magnitude signals being provided to said multiplicator, and multiplied by weighting factors supplied from said memory, before being provided to said second input of said first and second multiplicators.

4. Apparatus according to claim 1 wherein said fourth means includes adders each of which is provided with a feed back to function as a summator, first components of said vector valued signals being provided to and summed by one of said adders, and fourth components of said vector valued signals being provided to and summed by the other of said adders, the output of said adders providing said first vector valued output signal of said second means.

5. Apparatus according to claim 4, wherein said fourth means further includes a first multiplicator and a second multiplicator and a memory, said first components being multiplied in said first multiplicator by weighting factors supplied from said memory, and said second components being multiplied in said second multiplicator by weighting factors supplied from said memory, before said first and second components are provided to said adders.

6. Apparatus according to claim 1 wherein said fourth means includes a first implementing means coupled to a first summator, and a second implementing means coupled to a second summator, and wherein said fourth means sums up all of said first components multiplied by weighting factors that are implemented by said first implementing means subsequent to which first resulting signals are passed from said first implementing means to said first summator, and wherein said fourth means sums up all of said second components multiplied by weighting factors that are implemented by said second implementing means subsequent to which second resulting signals are passed from said second implementing means to said second summator, said first and second summators thereby providing said first vector valued output signal of said fourth means.

7. Apparatus according to claim 1 wherein said fifth means includes an adder provided with a feed back which functions as a summator, magnitude signals of said vector valued signals being provided to an input of said adder, the output of said adder providing said second output signal of said fifth means.

8. Apparatus according to claim 7, wherein said fifth means further includes a multiplicator and a memory, said magnitude signal being multiplied in said multiplicator, by weighting factors supplied from said memory, and then provided to said adder.

9. Apparatus according to claim 1 wherein said fifth means includes an implementing means coupled to a summator, and wherein said fifth means sums up all of the components of magnitude signals, of said vector valued signals, multiplied by weighting factors implemented by said implementing means, subsequent to which the resulting signals are passed to said summator, said summator thereby providing said second output signal of said fifth means.

10. Apparatus according to claim 1 wherein said fifth means includes a first multiplicator and a second multiplicator, said first and second multiplicators being coupled to a first adder which is coupled to a unit which is coupled to a second adder which is provided with a feed back to function as a summator, first components of said vector valued signals being provided toinputs of said first multiplicator for squaring and second components of said vector valued signals being provided to inputs of said second multiplicator for squaring, the output signals of said first and second multiplicators being provided to the input of said first adder for summing, the output signals of said first adder being provided to the input of said unit for forming the square root of said output signals of said first adder, the output signals of said unit being provided to the input of said second adder for adding to produce said second output signal of said fifth means.

11. Apparatus according to claim 10 wherein said fifth means includes a third multiplicator and a fourth multiplicator, said third and fourth multiplicators being coupled to a memory, said third multiplicator also being coupled to said first multiplicator and said fourth multiplicator also being coupled to said second multiplicator, said first components being provided to the input of said third multiplicator for multiplying by a weighting factor supplied from said memory and then being provided to said inputs of said first multiplicator, and said second components being provided to the input of said fourth multiplicator for multiplying by a weighting factor supplied from said memory and then being provided to said inputs of said second multiplicator.