Mask-surrogate semiconductor process employing dopant protective region

• US 4,748,103 A
• Filed: 03/21/1986
• Issued: 05/31/1988
• Est. Priority Date: 03/21/1986
• Status: Expired due to Term

• Current Assignee: Advanced Power Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Advanced Power Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Hollinger, Theodore G.
• Primary Examiner(s): Kittle, John E.
• Assistant Examiner(s): Dees, Jose G.
• Application Number:
  US06/842,771
• Time in Patent Office: 802 Days
• Field of Search: 430/313, 430/317, 430/314, 430/945, 430/311, 250/492.21, 250/492.3, 148/187, 29/578, 437/28, 437/930, 437/29, 437/931, 437/34, 437/933, 437/36, 437/40, 437/41, 437/147, 437/150, 437/157, 437/229, 437/907, 437/913, 437/984, 437/986
• US Class Current: 430/314
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 430/146 Laser beam
• CPC Class Codes: Y10S 438/942 Masking

Abstract

A mask-defect-immune process for making MOS semiconductor devices. The process features the creation of a surrogate mask in semiconductor wafer material per se, thus to eliminate the requirement that plural masks be used, and that plural mask alignments be performed. In all ways of practicing the invention, a surrogate mask is created in a dopant protective region.

Claims

1. A method employing no more than one independent mask of producing a plural-functional-region MOS semiconductor device in a substrate structure including an outer, MOS oxide layer, and wherein at least one doping step is involved, said method comprising

forming over the oxide layer a dopant protective layer,

creating a first and only mask-surrogate pattern-definer having a defined outline characteristic in such protective layer, and

thereafter, employing the unaltered perimetral outline characteristic per se of such only-created pattern-definer for control and self-alignment masking to effect the making of the desired, final functional regions in the device, including a conductive-material deposition step.

2. The method of claim 1, wherein said creating is accomplished in the absence of the use of any independent mask.

3. The method of claim 2, wherein said creating is performed by a controlled laser.

4. The method of claim 2, wherein said creating takes place through ion-beam bombardment.

5. The method of claims 1, 2, 3 or 4, wherein the making of the final functional regions includes at least one diffusion step.

11. The method of claim 1, wherein the making of the final functional regions includes at least one diffusion step.

6. A method of producing a plural-functional-region MOS semiconductor device in a substrate structure including an outer, MOS oxide layer, said method comprising

forming over the oxide layer a dopant protective layer,

in the absence of the use of any independent mask, creating a first and only mask-surrogate pattern-definer having a defined outline characteristic in such protective layer, and

thereafter, employing the unaltered perimetral outline characteristic per se of such only-created pattern-definer for control and self-alignment masking to effect the making of the desired, final functional regions in the device, including a conductive-material deposition step.

7. The method of claim 6, wherein said creating is performed by a controlled laser.

8. The method of claim 6, wherein said creating takes place through ion-beam bombardment.

9. The method of claims 6, 7 or 8, wherein the making of the final functional regions includes at least one doping step.

10. A method of producing a plural-functional-region MOS semiconductor device in a substrate structure including an outer MOS oxide layer, and wherein at least one doping step is involved, said method comprising

forming over the oxide layer a dopant protective layer,

creating, with a single, pre-configured, independent mask, a first and only mask-surrogate pattern-definer having a defined outline characteristic in such protective layer, and

thereafter, employing the unaltered perimetral outline characteristic per se of such only-created pattern-definer, in lieu of any other independent mask, for control and self-alignment masking to effect the making of the desired, final functional regions in the device.