LCD panel CMOS display circuit

• US 4,748,444 A
• Filed: 11/21/1985
• Issued: 05/31/1988
• Est. Priority Date: 11/22/1984
• Status: Expired due to Term

• Current Assignee: OKI Electric Industry Company Limited
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Arai, Yasuo
• Primary Examiner(s): Brigance, Gerald L.
• Assistant Examiner(s): Brier, Jeffery A.
• Application Number:
  US06/800,342
• Time in Patent Office: 922 Days
• Field of Search: 340/765, 340/784, 350/332, 350/333
• US Class Current: 345/99
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3622 using a passive matrix G09G3/3674 - G09G3/3696 take precedence

Abstract

An LCD panel display circuit for AC-driving a LCD panel with using a plurality of bias voltages has a display data interrupting circuit and an operation mode switching circuit, and the liquid crystal display panel includes a plurality of display cells having a plurality of X and Y electrodes arranged in a matrix form. The display data interrupting circuit interrupts the display data transmitted to the X and Y electrodes of the LCD panel in the operation mode thereof in which all of the display cells are in an inactive state. The operation mode switching circuit generates a control signal for allowing the same voltage to be applied to all of the X and Y electrodes of the LCD panel.

Claims

1. An LCD panel CMOS display circuit for line-scanning and controlling an LCD panel having a plurality of X and Y electrodes arranged in a matrix form and having a plurality of liquid crystal display cells between said X and Y electrodes, comprising:

(a) a timing control circuit for generating a serial scanning data signal, a serial display data signal, a first shift clock signal, a second shift clock signal, a first control signal, and a second control signal;

(b) a multi-power source for producing a first group of bias voltages and a second group of bias voltages;

(c) a scanning data converter coupled to said timing control circuit for sequentially converting said scanning data from said timing control circuit in response to said first shift clock signal so as to convert said scanning data into scanning data in a parallel form which are output on a plurality of output lines;

(d) a first gate having a plurality of output lines and coupled to said output lines of said scanning data converter for selectively transmitting said scanning data from said converter in response to said first control signal;

(e) an X-bias selection circuit coupled to said first gate and including a plurality of first decoders and a plurality of drivers, each of said plurality of decoders coupled to one of said output lines of said first gate for converting a signal supplied thereto into a specific coded signal in response to a third control signal, each of said plurality of drivers coupled to a different one of said plurality of decoders for delivering a specific one of said first group of bias voltages to one of said X electrodes of said LCD matrix panel in response to its specific coded signal;

(f) a display data holding circuit for converting said serial display data signal into parallel data in response to said second shift clock signal and for selectively outputting said parallel data on a plurality of output lines in response to said first shift clock signal;

(g) a second gate having a plurality of output lines and coupled to said output lines of said display data holding circuit for selectively transmitting said parallel data in response to said first control signal;

(h) a Y-bias selection circuit coupled to said second gate including a plurality of second decoders and a plurality of drivers, each of said plurality of decoders coupled to one of said output lines of said second gate for converting a signal supplied thereto into a specific coded signal in response to a fourth control signal, each of said plurality of drivers coupled to different one of said plurality of decoders for delivering a specific one of said second group of bias voltages to one of said Y electrodes of said LCD matrix panel in response to its specific coded signal; and

(i) a mode switching circuit coupled to said first and second pluralities of decoders for transmitting said second control signal to said first and second pluralities of decoders when said first control signal is in a first logic level, whereby said LCD panel is placed in a display mode, and for ceasing the transmission of said second control signal when said first control signal is in a second logic level, whereby the same bias voltage is provided to said X and Y electrodes of said LCD panel so as to place said LCD panel in a non-display mode.

2. An LCD panel CMOS display circuit according to claim 1, wherein said mode switching circuit comprises an OR gate circuit having an output coupled to said first plurality of decoders of said X-bias selection circuit, a first input for receiving said first control signal, and a second input for receiving said second control signal, and further comprises an AND gate circuit having an output coupled to said second plurality of decoders of said Y-bias selection circuit, a first input for receiving said first control signal, and a second input for receiving said second control signal;

and first gate comprises a plurality of OR gate circuits; and

said second gate comprises a plurality of OR gate circuits.

3. An LCD panel CMOS display circuit for line-scanning and controlling an LCD panel having a plurality of X and Y electrodes arranged in a matrix form and having a plurality of liquid crystal display cells between said X and Y electrodes, comprising:

(a) a timing control circuit for generating a serial scanning data signal, a serial display data signal, a first shift clock signal, a second shift clock signal, a first control signal, and a second control signal;

(b) a multi-power source for producing a first group of bias voltages and a second group of bias voltages;

(c) a scanning data converter coupled to said timing control circuit for sequentially converting said scanning data from said timing control circuit in response to said first shift clock signal so as to convert said scanning data into scanning data in a parallel form which are output on a plurality of output lines;

(d) an X-bias selection circuit coupled to said scanning converter and including a first plurality of decoders and a plurality of drivers, each of said plurality of decoders coupled to one of said output lines of said scanning data converter for converting a signal supplied thereto into a specific coded signal in response to said first control signal, each of said plurality of drivers coupled to a different one of said plurality of decoders for delivering a specific one of said first group of bias voltage in response to said specific coded signal;

(e) a first gate coupled to said X-bias selection circuit for selectively transmitting either specific bias voltages from said plurality of decoders or a different bias voltage to said X electrodes of said LCD panel in response to said second control signal;

(f) a display data holding circuit for converting said serial display data signal into a parallel display data in response to said second shift clock signal and for selectively outputting said parallel data or a plurality of output lines in response to said first shift clock signal;

(g) a Y-bias selection circuit coupled to said display data holding circuit and including a second plurality of decoders and a plurality of drivers, each of said plurality of decoders coupled to one of said output lines of said display data holding circuit for converting a signal supplied thereto into a specific coded signal in response to said first control signal, each of said plurality of drivers coupled to a different one of said plurality of decoders for delivering a specific one of said second group of bias voltages in response to its specific coded signal; and

(h) a second gate coupled to said Y-bias selection circuit for selectively transmitting either specific bias voltages from said plurality of decoders or said different bias voltage to said Y electrodes of said LCD panel in response to said second control signal, whereby said different bias voltage is supplied to said X and Y electrodes in a non-display mode of said LCD panel.

4. An LCD panel CMOS display circuit according to claim 3, wherein said first and second gates each comprise CMOS switches including P and N MOS transistors.