Deep polysilicon emitter antifuse memory cell
First Claim
1. An antifuse for a memory cell having at least two cell selection lines, comprising:
- a transistor decoupling element having a base, a collector, and a emitter comprising polysilicon;
one of said selection lines being located over the base of said transistor and in electrical contact therewith;
an initially nonconductive antifuse layer;
a refractory conductive layer beneath said nonconductive antifuse layer;
a silicide layer between said polysilicon of said emitter and said refractory conductive layer;
a nonrefractory metal layer on said antifuse layer;
said antifuse layer, said nonrefractory metal layer and said polysilicon of said emitter being in vertical alignment;
said nonrefractory metal layer providing another cell selection lines;
whereby metal from said nonrefractory metal layer diffuses through said antifuse layer to said refractory conductive layer upon application of a predetermined minimum potential between said nonrefractory layer and the base of said transistor to provide a conductive path between said nonrefractory layer and said emitter.
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Accused Products
Abstract
A memory cell (10) has a bipolr decoupling element (56), (68), (82), (92) having an exterior contact (36). A refractory conductive layer (40) is formed on contact (36), and an initially nonconductive antifuse layer (48) is formed on refractory layer (40). A nonrefractory metal layer (50) is formed on the nonconductive layer (48). Blocking elements (56) (68), (82) (92) are connected to a word line (52), (78). When a specified voltage is impressed across the nonrefractory metal layer (50) and the word line (52), (78), nonrefractory metal diffuses through the initially nonconductive layer (48) to the refractory conductive layer (40) to provide a conductive path between the two.
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Citations
14 Claims
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1. An antifuse for a memory cell having at least two cell selection lines, comprising:
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a transistor decoupling element having a base, a collector, and a emitter comprising polysilicon; one of said selection lines being located over the base of said transistor and in electrical contact therewith; an initially nonconductive antifuse layer; a refractory conductive layer beneath said nonconductive antifuse layer; a silicide layer between said polysilicon of said emitter and said refractory conductive layer; a nonrefractory metal layer on said antifuse layer; said antifuse layer, said nonrefractory metal layer and said polysilicon of said emitter being in vertical alignment; said nonrefractory metal layer providing another cell selection lines;
whereby metal from said nonrefractory metal layer diffuses through said antifuse layer to said refractory conductive layer upon application of a predetermined minimum potential between said nonrefractory layer and the base of said transistor to provide a conductive path between said nonrefractory layer and said emitter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An antifuse product for a memory cell made by a process comprising the steps of:
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providing a semiconductor substrate; forming a bipolar transistor decoupling element at least partially in said substrate and having a base, a collector, and an emitter comprising at least a doped polysilicon portion; forming, in vertical alignment with said doped polysilicon portion, a silicide layer atop the doped polysilicon portion, a refractory conductive layer atop said silicide layer, and initially insulating antifuse layer atop said refractory conductive layer, and a nonrefractory metal layer atop said antifuse layer; providing cell selection lines one of which being located above the base of the transistor in electrical contact therewith, the other being provided by said nonrefractory metal layer; whereby metal from the nonrefractory metal layer migrates through the antifuse layer to the refractory layer to short the antifuse layer upon application of a predetermined electric potential between the nonrefractory layer and the polysilicon portion. - View Dependent Claims (11, 12, 13, 14)
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Specification