Deep polysilicon emitter antifuse memory cell

• US 4,748,490 A
• Filed: 04/13/1988
• Issued: 05/31/1988
• Est. Priority Date: 08/01/1985
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hollingsworth, Deems R.
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US07/038,457
• Time in Patent Office: 48 Days
• Field of Search: 357/34.51, 357/59, 357/67, 357/71
• US Class Current: 257/530
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A memory cell (10) has a bipolr decoupling element (56), (68), (82), (92) having an exterior contact (36). A refractory conductive layer (40) is formed on contact (36), and an initially nonconductive antifuse layer (48) is formed on refractory layer (40). A nonrefractory metal layer (50) is formed on the nonconductive layer (48). Blocking elements (56) (68), (82) (92) are connected to a word line (52), (78). When a specified voltage is impressed across the nonrefractory metal layer (50) and the word line (52), (78), nonrefractory metal diffuses through the initially nonconductive layer (48) to the refractory conductive layer (40) to provide a conductive path between the two.

Claims

1. An antifuse for a memory cell having at least two cell selection lines, comprising:

a transistor decoupling element having a base, a collector, and a emitter comprising polysilicon;

one of said selection lines being located over the base of said transistor and in electrical contact therewith;

an initially nonconductive antifuse layer;

a refractory conductive layer beneath said nonconductive antifuse layer;

a silicide layer between said polysilicon of said emitter and said refractory conductive layer;

a nonrefractory metal layer on said antifuse layer;

said antifuse layer, said nonrefractory metal layer and said polysilicon of said emitter being in vertical alignment;

said nonrefractory metal layer providing another cell selection lines;

whereby metal from said nonrefractory metal layer diffuses through said antifuse layer to said refractory conductive layer upon application of a predetermined minimum potential between said nonrefractory layer and the base of said transistor to provide a conductive path between said nonrefractory layer and said emitter.

2. The antifuse of claim 1, wherein said silicide layer on said emitter is platinum silicide.

3. The antifuse of claim 1 wherein said refractory conductive layer is a titanium tungsten alloy.

4. The antifuse of claim 1 wherein said nonrefractory metal is aluminum.

5. The antifuse of claim 1 wherein said antifuse is of amorphous silicon.

6. The antifuse of claim 5 wherein said amorphous silicon is undoped.

7. The antifuse of claim 6 wherein said antifuse layer has a thickness between about 500 Å

and 3100 Å

.

8. The antifuse of claim 1 wherein said predetermined minimum voltage is between about 4 to about 12 volts.

9. The antifuse of claim 1 further comprising a substrate in which at least the base and collector of said transistor are located, and a contact to the base of the transistor from a top surface of the substrate.

10. An antifuse product for a memory cell made by a process comprising the steps of:

providing a semiconductor substrate;

forming a bipolar transistor decoupling element at least partially in said substrate and having a base, a collector, and an emitter comprising at least a doped polysilicon portion;

forming, in vertical alignment with said doped polysilicon portion, a silicide layer atop the doped polysilicon portion, a refractory conductive layer atop said silicide layer, and initially insulating antifuse layer atop said refractory conductive layer, and a nonrefractory metal layer atop said antifuse layer;

providing cell selection lines one of which being located above the base of the transistor in electrical contact therewith, the other being provided by said nonrefractory metal layer;

whereby metal from the nonrefractory metal layer migrates through the antifuse layer to the refractory layer to short the antifuse layer upon application of a predetermined electric potential between the nonrefractory layer and the polysilicon portion.

11. The antifuse product made by the process of claim 10 and further comprising annealing said doped polysilicon portion to diffuse dopant therefrom into said substrate.

12. The antifuse product made by the process of claim 10 and further comprising forming said nonrefractory metal layer substantially from aluminum.

13. The antifuse product made by the process of claim 10 and further comprising forming said antifuse layer of amorphous silicon.

14. The antifuse product made by the process of claim 10 and further comprising programming said antifuse by selectively applying a potential between said refractory metal layer and said polysilicon portion of between about four and twelve volts.