Video processor architecture with distance sorting capability

• US 4,748,572 A
• Filed: 12/05/1984
• Issued: 05/31/1988
• Est. Priority Date: 12/05/1984
• Status: Expired due to Term

• Current Assignee: L-3 Communications Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Singer Company (SVP Holdings Ltd.)
• Inventors: Latham, Roy W.
• Primary Examiner(s): Krass, Errol A.
• Assistant Examiner(s): Teska, Kevin J.
• Application Number:
  US06/678,207
• Time in Patent Office: 1,273 Days
• Field of Search: 364/518, 364/521, 364/522, 340/723, 340/729, 340/734, 340/747, 358/104, 434/38, 434/43
• US Class Current: 345/422
• CPC Class Codes: G06T 15/40 Hidden part removal

Abstract

The specification describes a way of using distance sorting in order not to require a prioritization of those polygons that are to be rendered prior to a pixel-by-pixel construction of an image. The video processor recalls the input data into the pixel processor at least a number of times equal to the number of objects to be displayed.

Claims

1. In a video processor, having as input a means for generating faces of objects, comprising:

a frame buffer means for storing distance-related data, occlusion mask data, and color component data;

a pixel data processor means connected to the frame buffer means and having

(i) means for receiving data from the face generating means;

(ii) connection means interfacing from the pixel processor means back with the face generating means by which the faces of objects are caused to be generated for an image to be displayed;

(iii) connection means interfacing from the frame buffer means back with the pixel processor means by which the data stored in the frame buffer means is computed and updated based upon an initial pass through the generated faces and upon at least one subsequent pass through the generated faces; and

a display interface connected to the frame buffer means for receiving subsequently scanned color component data from the frame buffer means and for generating signals to drive a visual display.

2. The video processor of claim 1 wherein said pixel data processor means includes a skip-over update processor circuit means to decrease the processing time required and thereby provide a saving in computational power.

3. The video processor of claim 2 including hierarchical memory means for storing values of sequentially-encountered distance-related data.

4. The video processor of claim 3 including comparison processor means connected to said hierarchical memory means for receiving, subdividing, and comparing input face data with extreme values.

5. The video processor of claim 4 including means to connect said skip-over update processor means to the input of said hierarchical memory means and means to connect said skip-over update processor means to receive input data from said comparison processor means.

6. The video processor of claim 2 wherein said skip-over update processor circuit means includes input means to receive two dimensional extant and distance-related data for such face of said image to be displayed.

7. The video processor of claim 1 including a face memory for storing the face data generated on the first pass and for supplying data on subsequent passes.

8. The video processor of claim 7 in which the frame buffer means is divided into two parts, an updatable part and a displayable part, in which the displayable part is connected to the display interface and the updatable part is connected to the pixel processor means and in which the updatable and the displayable parts are assigned alternately on each subsequent pass.