Processor utilizing reconfigurable process segments to accomodate data word length

• US 4,748,585 A
• Filed: 12/26/1985
• Issued: 05/31/1988
• Est. Priority Date: 12/26/1985
• Status: Expired due to Fees

• Current Assignee: Donald M. Chiarulli, Duncan A. Buell, W. G. Rudd
• Original Assignee: Louisiana State University and Agricultural College Baton Rouge Campus University
• Inventors: Chiarulli, Donald M., Buell, Duncan A., Rudd, W. G.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): MILLS, JOHN G
• Application Number:
  US06/817,814
• Time in Patent Office: 887 Days
• Field of Search: 364/900, 364/200
• US Class Current: 712/15
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 9/226 Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

An independently programmable, parallel processor for electronic computers for performing mathematical and logical operations is provided having an array of arithmetic-logic units which are interconnected so as to form dynamically reconfigurable segments of arithmetic-logic units within the array. These dynamically reconfigurable segments are formed by particular combinations of the arithmetic-logic units and are so combined with selective switching circuitry so as to provide the processor with its independent and parallel features.

Claims

1. A method of operating an electronic computer processor having a plurality of ALU'"'"'s which may be operated in combination to increase their effective word length comprising the steps of:

(a) synchronizing two or more of said ALU'"'"'s;

(b) connecting two or more of said ALU'"'"'s according to a field in a single instruction word, whereby each group of connected ALU'"'"'s and each isolated ALU define a segment having a data word length equal to the combined word length of each ALU in said segment;

(c) entering a separate operation code and a separate operand instruction for each of said ALU'"'"'s, said operation codes and said operand instructions being contained in a field in said single instruction word;

(d) generating a local status output for each of said ALU'"'"'s;

(e) converting each of said local status outputs to a binary status bit;

(f) resolving said binary status bits into a single-bit condition code;

(g) selecting a common, next instruction word address for said ALU'"'"'s based upon a status of a condition enable code which directs whether said selection is to be made unconditionally or whether said selection is to be made conditioned upon a status of said single-bit condition code.

2. A method according to claim 1 wherein said condition enable code is responsive to a field in said single instruction word.

3. A method according to claim 2 wherein said conversion of said local status bits is accomplished by operation of a local test mask for each ALU, said local test mask being responsive to a field in said single instruction word.

4. A processor according to claim 3, wherein:

(a) said binary status bits for each segment are resolved into a local condition code for each segment;

(b) said local condition codes are resolved into a single-bit condition code by operation of an AND combination or an OR combination in response to a field in said single instruction word.

5. A method according to claim 4 further comprising the step of entering a branching instruction into a sequencer, said branching instruction being contained in a field in said single instruction word, and said sequencer being in communication with said condition enable code and said single-bit condition code.

6. A method according to claim 5, wherein there is a single program for all of said ALU'"'"'s.