Very high-speed digital data bus

• US 4,748,617 A
• Filed: 12/20/1985
• Issued: 05/31/1988
• Est. Priority Date: 12/20/1985
• Status: Expired due to Fees

• Current Assignee: Network Systems Corp. (Oracle Corporation)
• Original Assignee: Network Systems Corp. (Oracle Corporation)
• Inventors: Drewlo, Kenneth G.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Scutch, III, Frank M.
• Application Number:
  US06/811,750
• Time in Patent Office: 893 Days
• Field of Search: 370/85, 370/110.1, 370/100, 370/4, 370/94, 370/96, 375/107, 375/117, 455/612, 340/825.5
• US Class Current: 398/98
• CPC Class Codes: H04L 12/44 Star or tree networks

Abstract

A time-division multiplexed, data communications system allowing multiple user devices, including super computer buses configured in a local network, and other existing network hierarchies to exchange digital data over extended distances at speeds heretofore unattainable. The system includes a plurality of intelligent nodes, termed "DATApipe™ adapters", which are coupled to a fiber optic bus. The DATApipe adapters function as interface devices between the fiber optic bus and the I/O processors which are used to couple the user devices and networks to the DATApipe adapters.

Claims

1. In a data communications system of the type including a communications medium, a plurality of geographically distributed nodes, modem means operatively coupling said nodes to said medium for permitting any one of said nodes to transmit messages to any other of said nodes in the system, said messages including a header block, a data block and a trailer block, any one of said nodes in said system being a conditionally designated bus reference for the purpose of synchronizing the transmission of said messages, the improvement comprising:

(a) means including said modem means for receiving a single signal bit stream representative of said message, there being a synchronization pattern of bits embedded in said header block defining a timing reference relative to a composite pipe cycle, a pipe cycle being a time interval comprising a plurality of slots, groups of said plurality of slots being assignable to said plurality of nodes;

(b) synchronization pattern detecting means in each of said nodes for detecting said synchronization pattern; and

(c) timing means in each of said nodes coupled to said bit pattern detecting means for establishing a valid time interval within said pipe cycle corresponding to the group of said plurality of slots assigned to a particular one of said plurality of nodes for transmission of said messages onto said medium from said particular node on a non-interfering basis with messages being transmitted over said medium from other of said nodes, said valid time interval (slots) being contiguously transmitted from separate nodes independent of the propagation delay of said communication medium and the transmission rate of said messages.

2. The data communications system as in claim 1 wherein said modem means includes means for separating clock information from said single serial bit stream, and means for transmitting said serial bit stream, bit-by-bit, to said nodes in synchronization with said clock information.

3. The data communications system as in claim 2 wherein each of said nodes includes serial-to-parallel converter means for framing said serial data stream into bit-parallel words of predetermined length, said serial-to-parallel converter being controlled by said clock information to create word boundaries for said bit-parallel words.

4. The data communications system as in claim 3 and further including means for appending a plurality of parity bits to each of said bit parallel words, and means for detecting errors in transmission of said synchronization pattern of bits embedded in said header block.

5. The data communications system as in claim 1 wherein said medium comprises an optical fiber.

6. The data communications system as in claim 1 wherein said timing means includes:

(a) a first register for storing a count value corresponding to the total length of said pipe cycle;

(b) counter means for periodically receiving said count value from said first register means;

(c) means in said nodes for decrementing said counter means at a fixed clock rate; and

(d) means detecting when the contents of said counter means reaches a predetermined value and producing a control signal for reloading said counter means with the contents of said first register means whereby pipe cycle marks of a predetermined time spacing are repetitively generated.

7. The communications system as in claim 6 and further including:

(a) means for detecting any difference in time between the pipe cycle marks repetitively generated in a node and pipe cycle marks from said bus reference node;

(b) means for determining whether said time difference exceeds a predetermined range value; and

(c) means for adjusting said fixed clock rate until said time difference is within said predetermined range value.

8. The communications system as in claim 7 wherein said means in said nodes for establishing said fixed clock rate comprises:

(a) a stable voltage controlled oscillator; and

(b) digital-to-analog converter means coupled to said voltage-controlled oscillator, said digital-to-analog converter receiving its input from said means for adjusting said fixed clock rate.

9. The communications system as in claim 8 wherein said means for adjusting said fixed clock rate comprises:

(a) a microprocessor including memory means for storing a plurality of interrupt routines;

(b) means responsive to said means for determining whether said time difference exceeds said predetermined range for generating an interrupt signal for said microprocessor; and

(c) means coupling said microprocessor to said digital-to-analog converter.

10. A data communications system comprising:

(a) a communications medium;

(b) a plurality of geographically distributed nodes;

(c) modem means operatively coupling said nodes to said medium for permitting any one of said modes to transmit messages to any other of said nodes in the system, one of said nodes in said system being conditionally designated as a bus reference, said bus reference providing timing information synchronizing the transmission of said messages between said nodes in predetermined slots within an overall pipe cycle, a pipe cycle being a time interval including a plurality of said slots with groups of said slots being individually assignable to said plurality of nodes;

(d) each of said nodes including;

(i) multiplexor means coupled to receive input digital data messages in serial bit stream form on a plurality of ports;

(ii) decoupling memory means coupled to said multiplexer means for temporarily storing said data messages at discrete addressable locations therein;

(iii) logical transmitter means coupled to said decoupling memory means, said logical transmitter means including means for sensing the presences of the groups of said slots assigned to that node for controlling the times that the data messages are applied to said communications medium; and

(iv) memory control means coupled to said decoupling memory means for managing the allocation of buffer regions in said decoupling memory for storing messages arriving from each of said plurality of ports and reading out said messages under control of said logical transmitter means.

11. The communications systems as in claim 10 wherein said memory control means comprises:

(a) stack pointer memory means for storing stack pointer words for each of said plurality of ports, each stack pointer word having an address field and a control field;

(b) port address generating means for conditionally enabling transfer of message words into and out of said decoupling memory from a multiplicity of ports in a specified sequence, said port address generating means providing an address to said stack pointer memory;

(c) stack memory means for storing for each of said ports a threaded list of stack entry words which define said buffer regions in said decoupling memory, each stack entry word comprising an address field containing the current sequential address for said decoupling memory, a length field defining the remaining number of words in a given buffer region of said decoupling memory, and a thread field defining the address of a subsequent one of said stack entry words;

(d) means responsive to a read of one of said stack entry words from said stack memory for incrementing said address field and decrementing said length field of said one of said stack entry words;

(e) means for sensing a predetermined value of said length field of said one of said stack entry words; and

(f) means responsive to said sensing means for transferring the current thread field into its respective stack pointer word such that said current thread field becomes the stack pointer address field, whereby message words are transferred into and out of their respective buffer regions in decoupling memory in a predetermined sequential order.

12. Apparatus as in claim 11 and further including microprocessor means coupled to said memory control means and to said port address generating means for periodically updating said address, length and thread fields of said stack pointer words such that a continuous pool of available buffer regions are defined in said decoupling memory means as messages are read out therefrom to said logical transmitter means.

13. The communications system as in claim 10 and further including slot processor means coupled in controlling relation to said logical transmitter means, said slot processor means including:

(a) slot memory means for storing words defining the length of each of a plurality of slots at addressable locations therein;

(b) slot number generating means coupled to said slot memory means for reading out slot length values therefrom;

(c) means for converting said slot length values read from said slot memory means to corresponding sequential time intervals delimited by slot marks;

(d) means for presenting said slot numbers and slot marks to said logical transmitter means; and

(e) means for detecting whether the received slot number is assigned to a given one of said plurality of nodes and for sending an enable signal to said memory control means for accessing message words from said decoupling memory for transmission over said transmission media from said given node during the time interval of the current slot number.

14. A data communication system including:

(a) a communications medium;

(b) a plurality of nodes geographically distributed along said medium, said nodes interfacing at least one input/out processor device to said medium, said input/out processor devices communicating with said nodes in word serial form, said words comprising data bits and control bits, one of said control bits being a flow bit;

(c) means in said nodes and in said input/output processor for regulating the transfer of said words between buffer memories contained in said nodes and input/out processor devices, including;

(i) first control means in said nodes for establishing the state of said flow bit of each outgoing serial word transmitted to said input/out processor device conditional upon the ability of said buffer memory in said node to accept additional incoming words;

(ii) second control means in said input/out processor devices for establishing the state of said flow bit of each outgoing serial word transmitted to said node conditioned upon the ability of said buffer memory in said input/out processor devices to accept additional incoming words; and

(iii) third control means in both said nodes and in said input/out processor devices for suspending the transmission of outgoing serial words from said nodes and input/out processor devices conditionally upon the state of said flow bits of incoming serial words to said nodes and input/out processor devices.

15. In a data communication system of the type including a communications medium, at least one node, means coupling said node to said medium for permitting said node to transmit messages over said medium, the improvement comprising:

(a) buffer memory means contained in said node for at least temporarily storing message words at addressable block locations therein;

(b) input/output processor means coupled to said node for transmitting messages to and receiving messages from said buffer memory means in said node;

(c) flow control means in said node for providing a flow signal to said input/output processor means which, when in a first state, indicates the availability in said buffer memory means of a sufficient number of said addressable block locations to store more than a single block of message words being sent from said input/output processor means and when in a second state indicates to said input/output processor means the availability in said buffer memory means of not more than a single addressable block location in which to store only a predetermined number of data words transmitted from said input/output processor means which are less than the number of words comprising a single block.

16. The data communication system as in claim 15 and further including:

(a) further buffer memory means contained in each of said input/output processor means for at least temporarily storing message words at addressable block locations therein;

(b) flow control means in said input/output processor means for providing a flow signal to said node to which said input/output processor means is connected which, when in a first state, indicates the availability in said further buffer memory means of a sufficient number of said addressable block locations to store more than a single block of message words being sent from said node and, when in a second state, indicates to said node the availability in said further buffer memory means of not more than a single addressable block location in which to store only a predetermined number of message words transmitted from said node which are less than the number of words comprising a single block.

17. The data communication system as in claim 16 and further including flow signal responsive means in said node and in said input/output processor means for inhibiting further transmission of said message words between said node and said input/output processor means following the entry of said message words into said single addressable block location upon detection of said flow signal being in said second state.