Telecommunications interface
First Claim
1. A telecommunications interface for receiving asynchronous input data packets at preselected input bit rates and employing preselected input protocols from one or more user sources and for retransmitting the input data at preselected output bit rates and employing preselected output protocols compatible with the requirements of one or more reeiving devices,said telecommunications interface comprising:
- a memory for storing data contained in said input data packets,input means for sequentially receiving said asynchronous input data packets, stripping said packets of protocol information, and sequentially writing said data contained in said input packets into said memory,an address generator for generating the address in said memory where each of said input data packets is stored,address storage means for storing in an organized fashion addresses generated by said address generator, andmeans for retrieving particular addresses from said address storage means, means for retrieving the data stored in said memory means at said retrieved addresses, and output processors for receiving said retrieved data and for retransmitting said retrieved data at said preselected bit rates and employing said preselected protocols to said receiving devices.
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Accused Products
Abstract
A telecommunications interface is disclosed. The inventive telecommunications interface is capable of collecting multiple asynchronous video, audio, graphic and data signals from a variety of different kinds of sources and retransmitting such signals in a suitable form for display or detection with one or more types of receiver equipment at one or more locations. The interface operates at rates ranging from several hundred bits per second to several gigabits per second.
The telecommunications interface includes a dual port RAM whose input and output operate asynchronously. Signals from the user sources are stripped of timing and source identification information and are written into the dual port RAM, while output processors read previously stored user signals out from the dual port RAM. The output processor appropriately format the retrieved signals, which are then transmitted to the receiver equipment.
262 Citations
13 Claims
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1. A telecommunications interface for receiving asynchronous input data packets at preselected input bit rates and employing preselected input protocols from one or more user sources and for retransmitting the input data at preselected output bit rates and employing preselected output protocols compatible with the requirements of one or more reeiving devices,
said telecommunications interface comprising: -
a memory for storing data contained in said input data packets, input means for sequentially receiving said asynchronous input data packets, stripping said packets of protocol information, and sequentially writing said data contained in said input packets into said memory, an address generator for generating the address in said memory where each of said input data packets is stored, address storage means for storing in an organized fashion addresses generated by said address generator, and means for retrieving particular addresses from said address storage means, means for retrieving the data stored in said memory means at said retrieved addresses, and output processors for receiving said retrieved data and for retransmitting said retrieved data at said preselected bit rates and employing said preselected protocols to said receiving devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A telecommunications interface for receiving input data packets from one or more user sources and for retransmitting the input data in a format compatible with and for use by one or more receiving devices,
said telecommunications interface comprising: -
a memory for storing said input data packets, input means for sequentially receiving said input data packets and sequentially writing said input packets into said memory, wherein each incoming data packet includes clock frequency data and user data and wherein said input means comprises clock recovery means for recovering the clock frequency data of each incoming data packet, clock means for maintaining the recovered clock frequency for the duration of each incoming packet, shift register means including at least first and second shift registers for receiving the user data in each incoming packet after the clock frequency data has been removed therefrom, said user data being clocked into said shift register means at a rate determined by said recovered clock frequency data, and means for writing said user data into said memory when said first or second shift register is full, an address generator for generating the address in said memory where each of said input data packets is stored, address storage means for storing in an organized fashion addresses generated by said address generator, and output means for retrieving particular addresses from said address storage means, for accessing the data stored in the said memory at said retrieved addresses, and for retransmitting said accessed data to a particular receiving device. - View Dependent Claims (12)
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13. A telecommunications interface for receiving input signals from one or more user sources and for retransmitting the input signals in a format compatible with and for use by one or more receiving devices, said telecommunications interface comprising
a dual port random access memory, input means for receiving said input signals from said user sources and for writing said input signals into said dual port random access memory, an address generator for generating the addresses in said random access memory where said input signals are stored, a plurality of first-in-first-out (FIFO) memories for storing the addresses generated by said address generator, routing means for routing the addresses of input signals from particular ones of said user sources to particular ones of said FIFO memories, a plurality of output processors, at least some of said output processors being associated with one or more of said FIFO memories, means for retrieving addresses from at least some of said FIFO memories, means for accessing the signals stored at said retrieved addresses in said dual port random access memory, means for routing the accessed signals to an output processor associated with the FIFO memory from which the address of said accessed signal was retrieved, said output processors being capable of retransmitting the accessed signals to particular ones of said receiving devices, and feedback means so that signals routed from said memory to one of said output processors can be rewritten in said dual port random access memory.
Specification