Circuit for detecting level of input voltage

• US 4,749,880 A
• Filed: 08/12/1985
• Issued: 06/07/1988
• Est. Priority Date: 08/10/1984
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Kobatake, Hiroyuki
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US06/764,919
• Time in Patent Office: 1,030 Days
• Field of Search: 307/355, 307/356, 307/362, 307/363, 307/350, 330/257, 330/288
• US Class Current: 327/78
• CPC Class Codes: G01R 19/16519 using FET's
• CPC Class Codes: H03K 5/2472 using field effect transistors H03K5/2436 takes precedence

Abstract

A circuit for detecting the level of an input voltage is disclosed, in which the input voltage is converted into a current and this current is compared with a reference current obtained by converting a reference voltage. To accomplish such circuit functions, this level detection circuit comprises means for converting the input voltage into a first current, means for converting the reference voltage into a second current, means for producing a third current relative to the first current, means for producing a fourth current relative to the second current, and means for combining the third and fourth current. A detection output terminal is coupled to the combining means.

Claims

1. A transistor circuit comprising:

first and second potential terminals;

first and second input terminals;

first, second, third, and fourth nodes;

a first field effect transistor of a first conductivity type connected between said first potential terminal and said first node and having a gate connected to said first input terminal;

a second field effect transistor of said first conductivity type connected between said first potential terminal and said second node and having a gate connected to said second input terminal;

a third field effect transistor of a second, opposite conductivity type, connected between said second potential terminal and said first node and having a gate connected to said first node;

a fourth field effect transistor of said second conductivity type connected between said second potential terminal and said third node and having a gate connected to the gate of said third transistor;

a fifth field effect transistor of said second conductivity type connected between said second potential terminal and said second node and having a gate connected to said second node;

a sixth field effect transistor of said second conductivity type connected between said second potential terminal and said fourth node and having a gate connected to the gate of said fifth transistor;

a seventh field effect transistor of said first conductivity type connected between said fourth node and said first potential terminal and having a gate connected to said fourth node;

an eighth field effect transistor of said first conductivity type connected between said third node and said first potential terminal and having a gate connected to the gate of said seventh transistor;

means for supplying an input voltage to one of said first and second input terminals;

means for supplying a reference voltage to the other of said first and second input terminals;

an output terminal coupled to said third node;

a ninth field transistor of said first conductivity type connected in series with said first field effect transistor between said first potential terminal and said first node;

a tenth field effect transistor of said first conductivity type connected in series with said second field effect transistor between said first potential terminal and said second node; and

means for supplying a control signal to gates of said ninth and tenth field effect transistors, wherein said ninth and tenth field effect transistors are turned ON to enable said transistor circuit when said control signal takes a first logic level and turned OFF to disenable said transistor circuit when said control signal takes a second logic level.

2. A transistor circuit comprising first and second potential terminals, first, second, third, and fourth nodes, a first series connection circuit of first and second field effect transistors of a first conductivity type provided between said first potential terminal and said first node, a first input terminal connected to the gate of said first transistor, a second series connection circuit of third and fourth field effect transistors of said first conductivity type provided between said first potential terminal and said second node, a second input terminal connected to the gate of said third transistor, a fifth field effect transistor of a second, opposite conductivity type, connected between said second potential terminal and said first node and having a gate connected to said first node, a sixth field effect transistor of said second conductivity type connected between said second potential terminal and said third node and having a gate connected to the gate of said fifth transistor, a seventh field effect transistor of said second conductivity type connected between said second potential terminal and said second node and having a gate connected to said second node, an eighth field effect transistor of said second conductivity type connected between said second potential terminal and said fourth node and having a gate connected to the gate of said seventh transistor, a third series connection circuit of ninth and tenth field effect transistors of said first conductivity type provided between said third node and said first potential terminal, means for connecting the gate of said ninth transistor to said second potential terminal, a fourth series connection circuit of eleventh and twelfth field effect transistors of said first conductivity type provided between said fourth node and said first potential terminal, means for connecting the gate of said eleventh transistor to said fourth node and to the gate of said tenth transistor, an output terminal connected to said third node, a control terminal connected in common to the gates of said second, fourth and twelfth transistors, means for supplying an input voltage to one of said first and second input terminals, means for supplying a reference voltage to the other of said first and second input terminals, and means for supplying a control signal to said control terminal, said second, fourth, and twelfth transistors being turned on to enable said first, third, and eleventh transistors respectively when said control signal is at a first level, and being turned off to disenable said first, third, and eleventh transistors respectively when the control signal is at a second level.

3. The circuit as claimed in claim 2, further comprising a thirteenth field effect transistor of said second conductivity type connected between said first node and said second potential terminal and fourteenth field effect transistor of said second conductivity type connected between said fourth node and said second potential terminal, said control terminal being further connected to the gates of said thirteenth and fourteenth transistors.

4. A comparator comprising:

an input terminal receiving an input voltage;

a reference terminal receiving a reference voltage;

a first terminal receiving a first power voltage;

a second terminal receiving a second power voltage smaller than said first power voltage;

an output terminal;

first and second nodes;

a first P-channel field effect transistor connected between said first power terminal and said output terminal;

a second P-channel field effect transistor connected between said first power terminal and said first node and having a gate connected to said first node and to a gate of said first field effect transistor;

first converting means coupled to said input terminal for converting said input voltage into a first current;

means for supplying said first current to said first node;

a third N-channel field effect transistor connected between said second power terminal and said output terminal;

a fourth N-channel field effect transistor connected between said second power terminal and said second node and having a gate connected to said second node and to a gate of said third field effect transistor;

second converting means coupled to said reference terminal for converting said reference voltage into a second current; and

means for supplying said second current to said second node, said first and second field effect transistors constituting a first current mirror circuit, said third and fourth field effect transistors constituting a second current mirror circuit, wherein an output voltage of said output terminal is changed from a first level close to one of said first and second power voltages to a second level close to the other of said first and second power voltages when said input voltage exceeds said reference voltage.

5. A detection circuit for detecting whether an input voltage is larger than a positive power supply voltage, comprising:

a first input terminal supplied with said input voltage;

a first power terminal supplied with said positive power supply voltage;

a second power terminal supplied with a ground potential;

a second input terminal connected to said first power terminal;

first, second and third nodes;

an output terminal;

a first N-channel field effect transistor connected between said second power supply terminal and said first node and having a gate connected to said first input terminal;

a second P-channel field effect transistor connected between said first power terminal and said first node and having a gate connected to said first node;

a third P-channel field effect transistor connected between said first power terminal and said output terminal and having a gate connected to the gate of said second field effect transistor;

a fourth N-channel field effect transistor connected between said second power terminal and said second node and having a gate connected to said second input terminal;

a fifth P-channel field effect transistor connected between said first power terminal and said second node and having a gate connected to said second node;

a sixth P-channel field effect transistor connected between said first power terminal and said third node and having a gate connected to the gate of said fifth field effect transistor;

a seventh N-channel field effect transistor connected between said second power terminal and said third node and having a gate connected to said third node; and

an eighth N-channel field effect transistor connected between said second power terminal and said output terminal and having a gate connected to the gate of said seventh field effect transistor, wherein said circuit produces a detection output from said output terminal when said input voltage is larger than said positive power supply voltage by a predetermined value.