Printer-tape data link processor with DMA slave controller which automatically switches between dual output control data chomels

• US 4,750,107 A
• Filed: 01/07/1985
• Issued: 06/07/1988
• Est. Priority Date: 01/07/1985
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Buggert, Jerrold E.
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Lee, Thomas C.
• Application Number:
  US06/689,209
• Time in Patent Office: 1,247 Days
• Field of Search: 364/200, 364/900
• US Class Current: 710/21
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Abstract

A peripheral controller (data link processor) controls data transfers between a host computer and a plurality of tape peripheral units and a single printer peripheral unit. A master microprocessor commands three subordinate controllers to permit concurrent data transfers through a buffer memory in both the Read and the Write directions. A dual channel control from the master microprocessor actuates a DMA switch so that data transfers to/from the tape units can be controlled by switching on alternate control lines which regulate the data transfer operations.

Claims

1. A peripheral controller, designated as a data link processor, for controlling data transfer operations between a host computer, a printer peripheral unit, and a plurality of tape peripheral units, comprising:

(a) master microprocessor means for controlling a plurality of slave-controller means, said means including;

(a1) a master microprocessor for controlling operations of a DMA slave controller means, of a tape state machine slave controller means, of a printer state machine slave controller means, and of a data link interface (DLI) slave-controller means connected to a buffer memory means;

(a2) said DMA slave controller means for controlling data transfer to/from said tape peripheral units via said tape state machine slave controller means, said DMA slave controller means including;

(a2a) first and second output control data channels for transmitting control data to a tape interface means;

(b) a data link interface (DLI) means for connecting said host computer to said peripheral controller, and said buffer memory means, and including;

(b1) said data link interface (DLI) slave-controller means for controlling data transfer operations between said host computer and said buffer memory means;

(b2) said buffer memory means being alternately accessed by said master microprocessor means and said data link interface (DLI) slave-controller means, said buffer memory means being connected to said host computer via a DLI data bus and connected to a tape interface means and a printer interface means via a master microprocessor data bus;

(b3) said DLI data bus connecting said host computer via said DLI interface means to said buffer memory means;

(c) said tape interface means including;

(c1) said tape state machine slave-controller means for controlling data transfers between said buffer memory means and said plurality of tape peripheral units, said tape state machine slave-controller means including;

(c1a) means for automatically switching the control of data transfer operations between said first and second output control data channels;

(c1b) peripheral bus connection means to said plurality of tape peripherial units;

(c1c) means to generate, to said means for automatically switching, an end-of-transmission signal when a particular data transfer operation is terminated;

(d) said printer interface means connected to said buffer memory means via said master microprocessor means, said printer interface means including;

(d1) bus connection means to a peripheral printer unit;

(d2) a printer send-receive latch for temporary storage of data being transferred between said printer peripheral unit and said buffer memory means;

(d3) printer state machine slave controller means under command of said master microprocessor means and including;

(d31) means for controlling data transfers between said printer send-receive latch and said printer interface means;

(d32) means to control the allocation of tape data transfer requests from said DMA slave controller means and printer data transfer requests from said printer peripheral unit.

2. The peripheral controller of claim 1, wherein said means for automatically switching includes:

(a) DMA switch means for automatically switching the utilization of one said output control data channel to said other output control data channel, upon receipt of said end-of-transmission signal from said DMA slave controller, said DMA switch means connected to either of said first and second output control data channels via control signals from said DMA slave controller.

3. The peripheral controller of claim 2, wherein said DMA switch means includes:

(a) means to sense said end-of-transmission signal from said DMA slave controller upon termination of control data transfers in either of said first and second output control data channels;

(b) means to switch control data transfer operations to the other output control data channel from that just utilized;

(i) and wherein said master microprocessor means further includes;

(c) a DMA subcontroller for generating control data to said tape peripheral units for transmission to said DMA switch means via said first or second output control data channels.

4. A peripheral controller, designated as a data link processor for controlling data transfer operations between a host computer, a printer peripheral unit, and a plurality of tape peripheral units, comprising:

(a) master microprocessor means for controlling a plurality of slave-controller means, said means including;

(a1) a master microprocessor for controlling operations of a DMA slave controller means, of a tape state machine slave controller means, and of a data link interface (DLI) slave-controller means connected to a buffer memory means;

(a2) said DMA slave controller means for controlling data transfers to/from said tape peripheral units via said tape state machine slave controller means, said DMA slave controller means including;

(a2a) first and second output control data channels for transmitting control data to a tape interface means;

(a2b) a DMA subcontroller for generating control data to said tape peripheral units for transmission to a DMA switch means via said first or second output control data channels;

(b) a data link interface (DLI) means for connecting said host computer to said peripheral controller, and to said buffer memory means, and including;

(b1) said data link interface (DLI) slave-controller means for controlling data transfer operations between said host computer and said buffer memory means;

(b2) said buffer memory means being alternately accessed by said master microprocessor means and said data link interface (DLI) slave-controller means, said buffer memory means being connected to said host computer via a DLI data bus and connected to a tape interface means via a master microprocessor data bus;

(b3) said DLI data bus connecting said host computer via said DLI interface means to said buffer memory means;

(c) said tape interface means including;

(c1) said tape state machine slave-controller means for controlling data transfers between said buffer memory means and said plurality of tape peripheral units, said tape state machine slave-controller means including;

(c1a) means for automatically switching control of data transfer operations alternately between said first and second output control data channels, said automatically switching means including;

(i) said switch means for automatically switching the utilization of one said output control data channel to said other output control data channel, upon receipt of a end-of-transmission signal from said DMA slave controller means, said DMA switch means connected to either of said first and second output control data channels via control signals from said DMA slave controller means, and wherein said DMA switch means includes;

(i-a) means to sense said end--of--transmission signal from said DMA slave controller upon termination of control data transfers in either of said first and second output control data channels;

(i-b) means to switch the control data transfer operations to the other output control data channel from that channel just utilized;

(c1b) peripheral bus connection means to said plurality of tape peripherial units;

(c1c) means to generate, to said means for automatically switching, said end-of-transmission signal when a block of data has been transferred between said buffer memory means and said tape peripheral unit;

(d) a printer interface means connected to said buffer memory means via said master microprocessor means, said printer interface means including;

(d1) bus connection means to a peripheral printer unit;

(d2) a printer send-receive latch for temporary storage of data being transferred between said printer peripheral units and said buffer memory means;

(d3) printer state machine slave controller means under command of said master microprocessor means and including;

(e1) means for controlling data transfers between said printer send-receive latch and said printer interface means;

(e2) means to control the allocation of (i) tape data transfer requests from said DMA subcontroller, and (ii) printer data transfer requests from said printer peripheral unit.

5. The peripheral controller of claim 4 which includes:

(a) access control means for controlling access to said buffer means for placing in or removing data thereform, said access control means being controlled in alternate cycles by said DLI slave-controller means and said master microprocessor means.

6. The peripheral controller of claim 4 wherein said access control means includes:

(a) dual port control means for receiving control and address data from said master microprocessor means, said port control means including;

(a1) means to regulate the buffer memory means access time period permitted to said DLI slave-controller means and to said master microprocessor means;

(b) DLI-direct memory access means for receiving control and address data from said DLI slave-controller means.

7. The controller of claim 4 wherein said means for automatically switching control of data transfer operations includes:

(a) overrun detection means for signaling said master microprocessor when said first or second control data channels have not yet been initialized.