D/A converter capable of producing an analog signal having levels of a preselected number different from 2.sup.N and communication network comprising the D/A converter

• US 4,750,191 A
• Filed: 11/04/1985
• Issued: 06/07/1988
• Est. Priority Date: 11/06/1984
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yoshida, Yasuharu
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/794,662
• Time in Patent Office: 946 Days
• Field of Search: 375/4, 375/19, 375/25, 375/27, 375/38, 375/39, 370/110.1, 370/110.4, 340/347 DA, 332/9 R, 332/31, 371/43, 371/44, 371/46
• US Class Current: 375/264
• CPC Class Codes: H03M 1/664 Non-linear conversion not otherwise provided for in subgroups of H03M1/66
• CPC Class Codes: H04L 27/3411 reducing the peak to average power ratio or the mean power of the constellation; Arrangements for increasing the shape gain of a signal set

Abstract

In a digital-to-analog converter, a digital input signal of x bits is subjected to digital-to-analog conversion with at least two of x bit positions recognized as a common bit position and converted into analog levels of a number which is different from 2^x where x is an integer. At least one additional common bit position may be selected from the x bit positions except the common bit position. The digital input signal may be pre-processed by the use of a logic circuit prior to the digital-to-analog conversion so as to control the number of analog levels. The digital-to-analog converter is applicable to a modulator which produces a quadrature amplitude modulated signal having a circular arrangement of signal points on a phase plane. A demodulator comprises an analog-to-digital converter for converting the above-mentioned analog signal into a reproduction of the digital input signal.

Claims

1. A digital-to-analog converter for converting a digital input signal of x number of bits into an analog output signal, where is is an integer which is not smaller than three, and where x bits are consecutively placed at first through x-th bit positions, respectively, said analog output signal taking a plurality of levels, wherein the improvement comprises:

processing means responsive to said digital input signal for processing at least two of said x bit positions as a common bit position to produce a processed digital signal of x number of bits having said common bit position, whereby after said processing siad original digital input signal of x bits becomes a processed digital signal having the same x-number of bits; and

converting means for converting said processed digital signal into the analog output signal which takes the levels of a number which is different from 2^x.

2. A digital-to-analog converter as claimed in claim 1, wherein at least two bit positions of the remaining bit positions except said at least two bit positions are processed as an additional common bit position.

3. A digital-to-analog converter for use in converting a digital input signal of x bits into an analog output signal, where x is an integer which is not smaller than three, said x bits being consecutively placed at first through x-th bit positins, respectively, said analog output signal taking a plurality of levels, wherein the improvement comprises:

processing means responsive to said digital input signal for processing at least two of said x bit positions as a common bit position to produce a processed digital signal having said common bit position;

said processing means comprising;

means responsive to said digital input signal for recognizing said at least two of said x bit positions as said common bit position to produce a recognized signal of the x bits which include said common bit position and which are numbered from first through x-th bits;

means responsive to i-th and (i+1)-th bits of said recognized signal for modifying said (i+1)-th bit by said i-th bit into a modivied (i+1)-th bit with said i-th bit kept unchanged, to produce said i-th bit and said modified (i+1)-th bit, where i is an integer between unity and x, both exclusive;

means responsive to said i-th bit, said modified (i+1)-th bit, and the remaining bits of said recognized signal for producing said processed digital signal; and

converting means for converting said processed digital signal into the analog signal which takes the levels of a number which is different from 2^x.

4. A modulator for use in modulating a pair of quadrature-phase carrier signals by a first and a second digital input signal into an amplitude modulated analog signal, each of said first and second digital input signals being represented by N bits where N represents an integer which is not smaller than three, said amplitude modulated analog signal having an amplitude and phase specified by M² signal points on a phase plane where M is equal to 2^N, said M² signal points being divisible into normal and specific signal points in a square distribution and divisible into a first part for said normal signal points and a second part for dislocated signal points given by dislocating said specific signal points in a circular distribution, wherein the improvement comprises:

determining means responsive to said first and second digital input signals for determining whether said first and second digital input signals are representative of either of said normal and specific signal points to produce a control signal representative of either of said first and second parts;

code converting means responsive to said control signal and said first and second digital input signals for converting said first and second digital input signals with reference to said control signal into first and second converted digital signals each of which has a preselected number of bit positions different from said N bits to specify said circular distribution;

digital-to-analog converting means for individually converting said first and second converted digital signals into first and second analog signals, respectively, each of which takes amplitudes of a number which is different from 2^N, by processing at least two of said preselected number of bit positions as a common bit position; and

means for combining said first and second analog signals into said amplitude modulated analog signal.

5. A modulator as claimed in claim 4, wherein said code converting means comprises:

producing means responsive to said first and second digital input signals for producing first and second modified signals which are representative of said dislocated signal points and which correspond to said first and second digital input signals, respectively, said producing means being for further producing first and second additional control signals specifying said specific signal points in relation to said first and second digital input signals, respectively;

selecting means responsive to said control signal, said first and second digital input signals, and said first and second modified signals for selecting said first and second modified signals when said control signal is representative of said specific signal points and, otherwise, for selecting said first and second digital input signals; and

conversion means responsive to said first and second additional control signals and coupled to said selecting means for converting either of said first and second digital input signals and said first and second modified signals in consideration of said first and second additional control signals to produce said first and second converted signals.

6. A modulator as claimed in claim 5, wherein said conversion means carries out rotation symmetry conversion.

7. A demodulator for use in combination with the modulator of claim 4, said demodulator being supplied with reproductions of said first and second analog signals and comprising:

analog-to-digital converting means for converting said reproductions of the first and second analog signals into first and second reproduced digital signals corresponding to said first and second converted signals, respectively; and

means responsive to said first and second reproduced digital signals for producing first and second reproductions of said first and second digital input signals.