Semiconductor integrated circuit device having a multi-layered wiring board for ultra high speed connection

• US 4,751,482 A
• Filed: 10/20/1986
• Issued: 06/14/1988
• Est. Priority Date: 12/23/1983
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Narita, Hisatoshi, Fukuta, Masumi
• Primary Examiner(s): Wan, Gene
• Assistant Examiner(s): LEE, BENNY T
• Application Number:
  US06/920,938
• Time in Patent Office: 603 Days
• Field of Search: 333/247, 333/246, 357/74, 357/80, 174/52 R, 174/525, 361/399
• US Class Current: 333/247
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01061 Promethium [Pm]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

This invention relates to an ultra high speed semiconductor integrated circuit device, and in particular to a layout and connecting structure between lead terminals of a package and signal pads on a chip. The device includes a wiring board, positioned above the chip, which comprises an internal transmission line having a predetermined characteristic impedance on a dielectric insulating plate. The internal transmission line forms a strip line or coplanar transmission line including a signal line an ground conductor film. The wiring board internconnects the outer lead and bonding pads on the chip. The wiring between the internal transmission lines can cross by using a multi-layered structure. As the result of the structure of the present invention, transmission loss is reduced, and it is possible to design the wiring board having an optimum performance for ultra high speed operation of the high density integrated circuit device.

Claims

1. A semiconductor integrated circuit device comprising:

package means;

a semiconductor chip having at least an output terminal and being mounted in said package means;

at least an outer lead extending from said package means; and

a wiring board mounted on said package means in opposing relationship to said semiconductor chip to seal said semiconductor chip therein, said wiring board comprising at least one dielectric plate and an internal transmission line fabricated on said dielectric plate, said internal transmission line comprising at least one ground conductor and at least one signal line spaced from said ground conductor, wherein said internal transmission line has a predetermined characteristic impedance determined by the width of said signal line, the dielectric constant of said dielectric plate, and the spacing between said signal line and said ground conductor, and wherein said internal transmission line extends over said semiconductor chip, and the signal line has at least a projection which directly interconnects said output terminal of said semiconductor chip and said outer lead.

2. A semiconductor integrated circuit device according to claim 1, wherein said internal transmission line is a coplanar guide, having said signal line and said ground conductor formed on a common surface of said dielectric plate.

3. A semiconductor integrated circuit device according to claim 1, wherein said internal transmission line is a strip line structure having said signal line formed on a surface of said dielectric plate opposing said semiconductor chip and said ground conductor formed on a surface of said dielectric plate remote from said semiconductor chip.

4. A semiconductor integrated circuit device according to claim 3, wherein said internal transmission line includes an impedance matching resistor mounted on said dielectric plate, and connected between said signal line and said ground conductor.

5. A semiconductor integrated circuit device according to claim 1, wherein said wiring board comprises a multi-layered wiring board.

6. A semiconductor integrated circuit device according to claim 5, wherein said multi-layered wiring board comprises plural dielectric plates with signal lines and ground conductors on each of said plates, and wherein said signal lines on said plates are interconnected with signal lines on said other plates through holes formed in each of said dielectric plates.

7. A semiconductor integrated circuit device comprising:

package means;

a semiconductor chip having at least an output terminal and being mounted in said package means;

at least an outer lead extending from said package means; and

a wiring board mounted on said package means in opposing relationship to said semiconductor chip said wiring board comprising a dielectric plate and an internal transmission line fabricated on said dielectric plate, said internal transmission line comprising a ground conductor and a signal line spaced from said ground conductor, wherein said internal transmission line has a predetermined characteristic impedance determined by the width of said signal line, the dielectric constant of said dielectric plate, and the spacing between said signal line and said ground conductor, and wherein said internal transmission line extends over said semiconductor chip, and the signal line directly interconnects said output terminal of said semiconductor chip and said outer lead;

wherein said internal transmission line is a strip line structure having said signal line formed on a surface of said dielectric plate opposing said semiconductor chip and said ground conductor formed on a surface of said dielectric plate remote from said semiconductor chip, and

wherein said internal transmission line includes a wave reforming circuit mounted on said remote surface of said dielectric plate and connected through a hole in said dielectric plate and coupled in series to said signal line.