Digital frequency synthesizer

• US 4,752,902 A
• Filed: 07/08/1985
• Issued: 06/21/1988
• Est. Priority Date: 07/08/1985
• Status: Expired due to Term

• Current Assignee: Sciteq Communications, Inc. (DZS, Inc.)
• Original Assignee: Sciteq Electronics, Inc. (DZS, Inc.)
• Inventors: Goldberg, Bar-Giora
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US06/752,823
• Time in Patent Office: 1,079 Days
• Field of Search: 364/721, 328/14, 379/418
• US Class Current: 708/276
• CPC Class Codes: G06F 1/0328 in which the phase increment is adjustable, e.g. by using an adder-accumulator

Abstract

N stages of BCD adders receive as a first addend BCD encoded information representing a desired frequency. They receive as a second addend the outputs of N stages of four-bit registers. The summing outputs of the adders are input data for the registers. The data is clocked into the register by a stable frequency source. The outputs from a plurality of the most significant stages of the registers are used to address a ROM. Using the periodically changing BCD address, a sinusoidal function is retrieved in individual samples from the ROM. Digital data from the ROM is converted to analog. A low pass filter enhances the desired frequency and suitably attenuates higher frequencies. An equalizer compensates for power roll-off.

Claims

1. A synthesizer of a periodic signal of selectable frequency comprising:

(a) a means for adding two binary-coded decimal addends, the sum of the two addends being a binary-coded decimal number,

(b) a means for remembering a binary-coded decimal number derived from and uniquely corresponding to a selected synthesizer output frequency, and continuously applying said decimal number as a first addend to said adding means,

(c) a means for storing said sum from said adding means in response to a clock signal, the stored sum being fed back to the adding means as a second addend,

(d) a means for providing the form of a signal being synthesized expressed as a ordered set of digitized samples of the signal, the samples being provided in response to stored sums in truncated form, one sample provided per truncated stored sum, the value of each sample so provided corresponding to a magnitude of said signal at the point in time that said sample is provided,

(e) a means for providing to the sum storing means a train of clock signals,

(f) a means for converting the provided samples to corresponding analog levels, and

(g) a means for filtering the analog levels to produce a generally continuous signal of the selected frequency.

2. The synthesizer according to claim 1 wherein the means for storing the sums comprises a register having a plurality of decimal digit stages.

3. The synthesizer according to claim 1 wherein the means for providing the samples comprises a memory having stored therein the form of the signal being synthesized, the form being expressed as a set of digitized samples of the magnitude of the signal, the samples being uniformly spread over a full cycle of the signal, the samples being stored in order in said memory at arithmetically progressive, binarycoded decimal addresses and each sample being individually recallable in response to its corresponding address.

4. The synthesizer according to claim 3 wherein the means for storing the sums comprises a register having a plurality of decimal digit stages.

5. A synthesizer of a periodic signal of selectable frequency comprising:

(a) a memory having stored therein the form of the signal being synthesized, the form being expressed as a set of digitized samples of the magnitude of the signal, the samples being uniformly spread over a full cycle of the signal, the samples being stored in order in said memory at arithmetically progressive, binary-coded decimal addresses and each sample being individually recallable in response to its corresponding address,

(b) a binary-coded decimal adder having inputs for two addends, the sum of the two addends being a binary-coded decimal number, the addends and the sum each having some number N decimal digits,

(c) a means for remembering a binary-coded decimal number derived from and uniquely corresponding to a selected synthesizer output frequency, and continuously applying said decimal number as a first addend to said adding means,

(d) a storage register for storing the sum from the adder in response to a clock signal, the stored sum being fed back to the adder as a second addend, each stored sum being communicated in truncated form to the memory as an address for recalling a sample,

(e) a digital to analog converter for coverting each sample recalled from the memory to a corresponding analog level,

(f) a source of a uniform train of clock signals which are communicated to the storage register, and

(g) a filter for removing undesirable frequency components from the analog levels to produce a generally continuous signal of the selected frequency.

6. The synthesizer according to claim 5 wherein the samples are stored in said memory at successive addresses and the number of samples is equal to the number ten raised to a power equal to the number of decimal digits in a memory address.

7. The synthesizer according to claim 5 wherein the memory is a binary addressable memory in which the samples are stored only in those portions of the memory addressable by a binary-coded decimal address.