Transaction analyzer

• US 4,752,928 A
• Filed: 05/06/1985
• Issued: 06/21/1988
• Est. Priority Date: 05/06/1985
• Status: Expired due to Term

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Kirkpatrick, Donald C., Chapman, David D.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): BURNS, WILLIAM
• Application Number:
  US06/730,418
• Time in Patent Office: 1,142 Days
• Field of Search: 324/73 R, 324/73 AT, 371/15, 371/18, 371/25, 371/26, 371/57, 371/60, 371/16, 371/27
• US Class Current: 714/39
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers

Abstract

A transaction analyzer, for use in conjunction with a data acquisition system having a probe for accessing binary data, i.e. address and control signals appearing at the terminals of an operating microprocessor, determines the type of processor transaction occurring based on sequences of state changes occurring on a selected set of the control signals so accessed. The transaction analyzer then generates a binary number representing the transaction type which may be acquired by the acquisition system in conjunction with the data accessed by the probe. The transaction analyzer, which uses an asychronous state machine, also generates control signals used by the acquisition system to clock data storage along with a signal to control the direction of flow of data signals between the processor and the acquisition system. The transaction analyzer is programmable such that it may be used with a variety of different types of microprocessors which may be accessed by the probe, even though such microprocessors may generate differing control line state change patterns during processor transactions and even though transaction types may vary from processor to processor.

Claims

1. A transaction analyzer, for use in conjunction with a data acquisition system accessing a set of digital signals appearing at a plurality of terminals of an electronic device, the electronic device being capable of executing a plurality of types of transactions, comprising:

an asynchronous state machine generating a control signal to initiate acquisition by the data acquisition system of data transmitted by the set of digital signals during the occurrence of one of the types of transactions, the occurrence and type of transaction being ascertained by monitoring indicative data patterns transmitted by a subset of the set of digital signals, a unique data pattern being associated with each type of transaction, the subset of the set of digital signals being applied as inputs to the state machine and the control signal being generated according to a current output state of the state machine.

10. A transaction analyzer as in claim 1 wherein said asynchronous state machine comprises:

first means to store a current machine state and a current output state, said first control signal being generated according to said current output state,

second means to generate a next machine state and a next output state, said next machine and output states being determined by said current machine state and said first signal subset, said first means storing said next machine and output states in place of said current machine and output states in response to an applied state change signal, and

third means to generate said state change signal a selected time following a change in state of said first signal subset.

11. A transaction analyzer as in claim 10 further comprising:

fourth means to generate a timing signal, said timing signal varying according to the current machine state, said selected time varying according to said timing signal.

12. A state machine as in claim 10 wherein said second means comprises an addressable memory device, said memory device being currently addressed according to a current state of said first signal subset in combination with said current machine state, and wherein said next machine and next output states are stored in said memory at a selected address.

2. A transaction analyzer, for use in conjunction with a data acquisition system accessing a set of digital signals appearing at a plurality of terminals of an electronic device under test, the electronic device under test being capable of executing a plurality of types of transactions, comprising:

a state machine having a current state and a next state, the next state being a function of the current state, a subset of the set of digital signals, and pre-programmed instructions; and

an output state register having data locations that are addressed by the current state of the state machine, the data locations containing data tages associated by the pre-programmed instructions with the type of transaction, so that the data acquisition system is informed of the type of transaction occurring in the electronic device under test by the associated data tag in a way that is uniform for the data acquisition system.

3. A transaction analyzer as recited in claim 2, wherein the state machine is asynchronous, operating independently of an externally generated synchronizing clocking signal.

4. A transaction analyzer as recited in claim 2, further comprising means for generating a timing signal dependent on the current state of the state machine.

5. A transaction analyzer as recited in claim 2, further comprising means fo generating a bi-directional control signal dependent on the current state of the state machine.

6. A transaction analyzer, for use in conjunction with a data acquisition instrument accessing a set of digital signals from one of a plurality of different microprocessors under test, the microprocessors under test each being capable of executing a plurality of types of transactions, comprising:

a state machine having a current state and a next state, the next state being a function of the current state, a subset of the set of digital signals, and pre-programmed instructions specific to the one of a plurality of microprocessors under test; and

an output state register having data locations that are addressed by the current state of the state machine, the data locations containing data tags associated by the pre-programmed instructions with the types of transactions of a particular microprocessor under test, so that the data acquisition instrument is informed of the type of transaction occurring in the particular microprocessor under test by the associated data tag in a way that is uniform for the data acquisition instrument despite differences between the plurality of microprocessors under test.

7. A transaction analyzer as recited in claim 6, wherein the state machine is asynchronous, operating independently of an externally generated synchronizing clocking signal.

8. A transaction analyzer as recited in claim 6, further comprising means for generating a timing signal dependent on the current state of the state machine.

9. A transaction analyzer as recited in claim 6, further comprising means for generating a bi-directional control signal dependent on the current state of the state machine.

13. A method for analyzing the transactions occurring in a a microprocessor of a particular type and informing a data acquisition system of the type of transaction occurring at each of a plurality of data acquisition times using a set of descriptions for transaction types that is the same for a variety of microprocessor types, the method comprising the steps of:

pre-programming a specialized state machine with reference information specific to the particular microprocessor from which data is to be acquired, the pre-programmed reference information describing in terms of transaction types the significance of various sequences of combinations of signals from microprocessors of that particular type,

monitoring the microprocessor with some of the inputs to the state machine,

comparing the activities of the microprocessor with the pre-programmed reference information to determine the transaction type presently occurring in the microprocessor, and

outputting data tages to the data acquisition system for association with the data acquired by the data acquisition system so as to classify the current transaction type according to the pre-programmed reference information into one of a set of descriptions of standard transaction types that embrace all of the types of transactions expected within any of the types of microprocessors within the variety of microprocessor types from which data is to be acquired.

14. A method as recited in claim 13, further comprising the step of outputting a timing signal dependent on the transaction type, the microprocessor type, and the pre-programmed reference information.

15. A method as recited in claim 13, further comprising the step of outputting a bi-directional control signal dependent on the transaction type, the microprocessor type, and the pre-programmed reference information.

16. A transaction analyzer for use with a data acquisition system to determine the type of transaction being performed by a processor in a device under test comprising:

means for monitoring a selected subset of a set of control lines from the processor;

means for recognizing from the selected subset a specific transaction type being performed by the processor, said recognizing means being programmable according to the processor in the device under test;

means for controlling acquisition of data from the processor by the data acquisition system according to the specific transaction type; and

means for providing to the data acquisition system a tag signal corresponding to the specific transaction type, the tag signal being independent of the processor.