Self-diagnosable integrated circuit device capable of testing sequential circuit elements

• US 4,754,215 A
• Filed: 11/05/1986
• Issued: 06/28/1988
• Est. Priority Date: 11/06/1985
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kawai, Masato
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Burns, W.
• Application Number:
  US06/927,038
• Time in Patent Office: 601 Days
• Field of Search: 371/15, 371/25, 371/27, 364/737, 324/73 R, 324/73 AT
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318522 Test of Sequential circuits test of microprocessors G06F11/2236, test of ALU's G06F11/2226
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

In a self-diagnosable integrated circuit device comprising sequential circuit elements in an internal logic circuit, a first test pattern signal is successively produced in a test mode from a test pattern generating circuit and stored into the sequential circuit elements with a first timing signal given from a timing signal generating circuit to the internal logic circuit. After storage of the first test pattern signal into the sequential circuit elements, a second test pattern signal is produced from the test pattern generating circuit with a second timing signal given to the internal logic circuit. The internal logic circuit carries out processing operations determined for the second timing signal and produces an output data signal which is dependent on the first and the second test pattern signals and which is evaluated by an external circuit. Storage of the first test pattern signal may be made by forming a scan path through a gate circuit connected to each sequential circuit element. Alternatively, each sequential circuit element may be loaded with the first test pattern signal by assigning addresses to the respective sequential circuit elements and by indicating each address.

Claims

1. A self-diagnosable integrated circuit device selectively operable in a normal mode and a test mode, said device being self-diagnosable in said test mode and comprising:

an internal logic circuit which includes sequential circuit elements and non-sequential circuit elements and which carries out processing operations by the use of said sequential and said non-sequential circuit elements in response to an internal input signal and an internal timing signal;

a data input terminal for an input data signal;

a control terminal for a control signal indicative of said processing operations;

a mode signal terminal for a mode signal representative of a selected one of said normal and said test modes;

test pattern generating means responsive to said mode signal for generating a first and a second test pattern signal determined for said sequential circuit elements and said processing operations of said internal logic circuit, respectively;

first selecting means coupled to said data input terminal and said test pattern generating means for selecting said input data signal and said second test pattern signal in said normal and said test modes, respectively, to produce a first selected signal;

first signal supplying means for supplying said first selected signal to said internal logic circuit as said internal input signal;

timing signal generating means responsive to said mode signal for generating a first and a second timing signal determined in relation to said sequential circuit elements and said control signal, respectively, when said mode signal is indicative of said test mode;

second selecting means coupled to said control terminal and said timing signal generating means for selecting said control signal and said second timing signal in said normal and said test modes, respectively, to produce a second selected signal;

second signal supplying means for supplying said second selected signal to said internal logic circuit as said internal timing signal; and

assigning means in said internal logic circuit for assigning said first test pattern signal to said sequential circuit elements in response to said first timing signal in said test mode.

2. A self-diagnosable integrated circuit device as claimed in claim 1, wherein said test pattern generating means comprises:

a first pattern generator responsive to said mode signal for generating said first test pattern signal; and

a second pattern generator responsive to said mode signal for generating said second test pattern signal.

3. A self-diagnosable integrated circuit device as claimed in claim 1, wherein said timing signal generating means comprises:

enable signal producing means responsive to said mode signal for producing a first enable signal and a second enable signal following said first enable signal when said mode signal is representative of said test mode;

first generating means responsive to said first enable signal for generating said first timing signal; and

second generating means responsive to said second enable signal for generating said second timing signal.

4. A self-diagnosable integrated circuit device as claimed in claim 1, wherein said assigning means comprises:

gate means responsive to said first test pattern signal and said first timing signal for sending said first test pattern signal to said sequential circuit elements only when said first timing signal is present; and

means for successively transferring said first test pattern signal to said sequential circuit elements to assign said first test pattern signal thereto.