High voltage semiconductor device

• US 4,754,310 A
• Filed: 12/04/1984
• Issued: 06/28/1988
• Est. Priority Date: 12/10/1980
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Coe, David J.
• Primary Examiner(s): Carroll, J.
• Application Number:
  US06/678,365
• Time in Patent Office: 1,302 Days
• Field of Search: 357/13, 357/20, 357/22, 357/23.4, 357/23.8, 357/34-36, 357/38, 357/42, 357/55, 357/65, 357/68, 357/86, 357/80, 357/14, 357/15
• US Class Current: 257/287
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 29/868 PIN diodes

Abstract

A field effect transistor, a bipolar transistor, a PIN diode, a Schottky rectifier or other high voltage semiconductor device comprise a semiconductor body having a depletion layer formed throughout a portion in at least a high voltage mode of operation of the device, such as, by reverse biasing a rectifying junction. The known use of a single high-resistivity body portion of one conductivity type to carry both the high voltage and to conduct current results in a series resistivity increasing approximately in proportion with the square of the breakdown voltage. This square-law relationship is avoided by the present invention in which a depleted body portion comprising an interleaved structure of first and second regions of alternating conductivity types carries the high voltage which occurs across the depleted body portion. The thickness and doping concentration of each of these first and second regions are such that when depleted the space charge per unit area formed in each of these regions is balanced at least to the extent that an electric field resulting from any imbalance is less than the critical field strength at which avalanche breakdown would occur in the body portion. The first regions in at least one mode of operation of the device provide electrically parallel current paths extending through the body portion.

Claims

1. A high voltage semiconductor device comprising a semiconductor body having a barrier-forming means for providing a barrier with a portion of said semiconductor body, and electrode connection means for applying a voltage in excess of 100 volts across said barrier to form a depletion layer extending throughout said portion in at least a high voltage mode of operation, said portion comprising a plurality of first regions of a first conductivity type interleaved with a plurality of second regions of a second conductivity type, said first and second regions extending longitudinally traverse to said barrier, at least said first regions providing electrically parallel current paths extending through said portion transverse to said barrier in at least one mode of operation, said first and second regions being depleted of free charge-carriers across their thickness in said high voltage mode of operation to form interleaved positive and negative space charge regions, said positive and negative space charge regions serving to carry high voltage in excess of 100 volts by said depletion layer spreading from said barrier across said portion when depleted of free charge-carriers, said first and second regions having a length perpendicular to their thickness for carrying a voltage in excess of 100 volts across said portion when depleted of free charge carriers, said first and second regions each having a thickness and doping concentration to balance said space charge per unit area formed in each of said first and second interleaved regions when depleted of free charge-carriers by said depletion layer and carrying said voltage in excess of 100 volts, said space charge per unit area being balanced at least to such an extent that an electric field resulting from said space charge is less than a critical field strength at which avalanche breakdown would occur in said portion.

2. A device according to claim 1, wherein said interleaved first and second regions are layers extending substantially parallel to a major surface of said semiconductor body.

3. A device according to claim 2, wherein said electrode connection means include first connection means for electrically connecting said first regions and second connection means for electrically connecting said second regions, said first connection means and said second connection means being present in grooves in said major surface, said first and second connection means contacting respective first and second regions at side walls of said grooves.

4. A device according to claim 3, wherein said grooves have a V-shape cross section.

5. A device according to claim 1, wherein said doping concentration of each of said first and second regions is at least 2×

10¹⁶ cm^-3.

6. A device according to claim 1 or claim 2 or claim 3 or claim 4 or claim 5, wherein said first regions are electrically connected to each other by a third region of said first conductivity type, said third region adjoining said first regions at an area of said semiconductor body spaced from said barrier-forming means for forming said depletion layer.

7. A device according to claim 6, wherein said depletion layer is formed by a metal-based layer on one end of said first and second interleaved regions, said metal-based layer forming a Schottky junction with said first regions.

8. A device according to claim 6, wherein in one mode of operation current flows through said portion of said semiconductor body as minority carriers in at least said frist regions, said minority carriers being extracted across p-n junctions between said first and second interleaved regions upon switching operation to another mode.

9. A device according to claim 6, wherein said semiconductor body comprises a bipolar transistor, said first and second interleaved regions providing adjacent parts of a base and collector of said transistor.

10. A device according to claim 7, wherein said semiconductor body comprises a power rectifier diode, said first and second interleaved regions forming an intermediate region between an anode and cathode of said diode.

11. A device according to claim 10, wherein said semiconductor body is a plurality of superimposed semiconductor layers, said semiconductor layers providing said first and second interleaved regions, and said semiconductor layers being mounted on a dielectric substrate.

12. A device according to claim 6, wherein said semiconductor body comprises a junction-gate field effect transistor, said first and second interleaved regions being present between source and drain regions of said transistor, said first regions providing channel regions of said transistor, and said second regions being connected to a gate of said transistor, said second regions serving as extensions of said gate.

13. A device according to claim 12, wherein said gate is a further region of second conductivity type, said gate forming a p-n junction with one end of each of said first regions.

14. A device according to claim 12, wherein said semiconductor body is a plurality of superimposed semiconductor layers, said semiconductor layers providing said first and second interleaved regions, and said semiconductor layers being mounted on a dielectric substrate.

15. A device according to claim 6, wherein said semiconductor body comprises a first insulated-gate field effect transistor having a source, said source being separated from said first and second interleaved regions by a further region of second conductivity type, said transistor having at least one gate insulated from said further region for capacitively generating a conductive channel in said further region for charge carriers of said first conductivity type, said charge carriers flowing between said source and a drain of said transistor, said first and second interleaved regions being present between said further region and said drain, said first regions serving as extensions of said drain.

16. A device according to claim 15, wherein said semiconductor body further comprises a second insulated-gate field effect transistor being of complementary conductivity type to said first transistor, said second regions serving as extensions of a drain of said second transistor, and said second regions forming a p-n junction with another region of first conductivity type, said another region separating said first and second interleaved regions from a source of said second transistor, said second transistor having at least one gate insulated from said another region for capacitively generating a conductive channel in said another region for charge carriers of said second conductivity type to flow between said source and drain of said second transistor.

17. A device according to claim 15, wherein said semiconductor body is a plurality of superimposed semiconductor layers, said semiconductor layers providing said first and second interleaved regions, and said semiconductor layers being mounted on a dielectric substrate.

18. A device according to claim 6, wherein said semiconductor body comprises two circuit elements of complementary conductivity types, said two circuit elements being connected in an inverse parallel arrangement across said portion of said semiconductor body, said first and second interleaved regions providing electrically parallel current paths of one circuit element interleaved with electrically parallel current paths of the complementary circuit element.

19. A device according to claim 1 or claim 2 or claim 3 or claim 4, or claim 5 wherein said depletion layer is formed by a third region of said semiconductor body, said third region being of said second conductivity type and said third region forming a p-n junction with one end of each of said first regions.

20. A device according to claim 19, wherein in one mode of operation current flows through said portion of said semiconductor body as minority carriers in at least said first regions, said minority carriers being extracted across p-n junctions between said first and second interleaved regions upon switching operation to another mode.

21. A device according to claim 19, wherein said semiconductor body comprises a bipolar transistor, said first and second interleaved regions providing adjacent parts of a base and collector of said transistor.

22. A device according to claim 19, wherein said semiconductor body comprises a power rectifier diode, said first and second interleaved regions forming an intermediate region between an anode and cathode of said diode.

23. A device according to claim 22, wherein said semiconductor body is a plurality of superimposed semiconductor layers, said semiconductor layers providing said first and second interleaved regions, and said semiconductor layers being mounted on a dielectric substrate.

24. A device according to claim 19, wherein said semiconductor body comprises a junction-gate field effect transistor, said first and second interleaved regions being present between source and drain regions of said transistor, said first regions providing channel regions of said transistor, and said second regions being connected to a gate of said transistor, said second regions serving as extensions of said gate, and said gate comprising said third region of said second conductivity type.

25. A device according to claim 24, wherein said semiconductor body is a plurality of superimposed semiconductor layers, said semiconductor layers providing said first and second interleaved regions, and said semiconductor layers being mounted on a dielectric substrate.

26. A device according to claim 19, wherein said semiconductor body comprises a first insulated-gate field effect transistor having a source, said source being separated from said first and second interleaved regions by a further region of second conductivity type, said transistor having at least one gate insulated from said further region for capacitively generating a conductive channel in said further region for charge carriers of said first conductivity type, said charge carriers flowing between said source and a drain of said transistor, said first and second interleaved regions being present between said further region and said drain, said first regions serving as extensions of said drain.

27. A device according to claim 26, wherein said semiconductor body further comprises a second insulated-gate field effect transistor being of complementary conductivity type to said first transistor, said second regions serving as extensions of a drain of said second transistor, and said second regions forming a p-n junction with another region of first conductivity type, said another region separating said first and second interleaved regions from a source of said second transistor, said second transistor having at least one gate insulated from said another region for capacitively generating a conductive channel in said another region for charge carriers of said second conductivity type to flow between said source and drain of said second transistor.

28. A device according to claim 26, wherein said semiconductor body is a plurality of superimposed semiconductor layers, said semiconductor layers providing said first and second interleaved regions, and said semiconductor layers being mounted on a dielectric substrate.

29. A device according to claim 19, wherein said semiconductor body comprises two circuit elements of complementary conductivity types, said two circuit elements being connected in an inverse parallel arrangement across said portion of said semiconductor body, said first and second interleaved regions providing electrically parallel current paths of one circuit element interleaved with electrically parallel current paths of the complementary circuit element.

30. A device according to claim 1, wherein said depletion layer is formed by a metal-based layer on one end of said first and second interleaved regions, said metal-based layer forming a Schottky junction with said first regions.

31. A device according to claim 1, wherein in one mode of operation current flows through said portion of said semiconductor body as minority carriers in at least said first regions, said minority carriers being extracted across p-n junctions between said first and second interleaved regions upon switching operation to another mode.

32. A device according to claim 1, wherein said semiconductor body comprises a bipolar transistor, said first and second interleaved regions providing adjacent parts of a base and collector of said transistor.

33. A device according to claim 1, wherein said semiconductor body comprises a power rectifier diode, said first and second interleaved regions forming an intermediate region between an anode and cathode of said diode.

34. A device according to claim 1, wherein said semiconductor body comprises a junction-gate field effect transistor, said first and second interleaved regions being present between source and drain regions of said transistor, said first regions providing channel regions of said transistor, and said second regions being connected to a gate of said transistor, said second regions serving as extensions of said gate, and said gate comprising a third region of said second conductivity type.

35. A device according to claim 34, wherein said gate provides a p-n junction with one end of each of said first regions.

36. A device according to claim 1, wherein said semiconductor body comprises a first insulated-gate field effect transistor having a source, said source being separated from said first and second interleaved regions by a further region of second conductivity type, said transistor having at least one gate insulated from said further region for capacitively generating a conductive channel in said further region for charge carriers of said first conductivity type, said charge carriers flowing between said source and a drain of said transistor, said first and second interleaved regions being present between said further region and said drain, said first regions serving as extensions of said drain.

37. A device according to claim 36, wherein said semiconductor body further comprises a second insulated-gate field effect transistor being of complementary conductivity type to said first transistor, said second regions serving as extensions of a drain of said second transistor, and said second regions forming a p-n junction with another region of first conductivity type, said another region separating said first and second interleaved regions from a source of said second transistor, said second transistor having at least one gate insulated from said another region for capacitively generating a conductive channel in said another region for charge carriers of said second conductivity type to flow between said source and drain of said second transistor.

38. A device according to a claim 36, wherein said semiconductor body is a plurality of superimposed semiconductor layers, said semiconductor layers providing said first and second interleaved regions, and said semiconductor layers being mounted on a dielectric substrate.

39. A device according to claim 1, wherein said semiconductor body comprises two circuit elements of complementary conductivity types, said two circuit elements being connected in an inverse parallel arrangement across said portion of said semiconductor body, said first and second interleaved regions providing electrically parallel current paths of one circuit element interleaved with electrically parallel current paths of the complementary circuit element.

40. A device according to claim 1, wherein said plurality of first regions is at least two, and said plurality of second regions is at least two.

41. A device according to claim 1, wherein the total number of said first and second regions is at least four.

42. A device according to claim 1, wherein said semiconductor body further comprises a substrate upon which said first and second interleaved regions exist.

43. A device according to claim 42, wherein said substrate is of dielectric material.

44. A device according to claim 43, wherein said dielectric material is sapphire.

45. A device according to claim 42, wherein said substrate is of semiconductor material.

46. A device according to claim 45, wherein said semiconductor material is silicon.

47. A device according to claim 45, wherein said semiconductor material of said substrate is of said second conductivity type.

48. A device according to claim 2, wherein said semiconductor body comprises a plurality of superimposed semiconductor layers providing said first and second interleaved regions, said semiconductor layers being present on a semiconductor substrate of said second conductivity type, said substrate having a doping concentration and thickness such that space charge occurring under reverse bias in a depleted portion of said substrate substantially balances an opposite space charge in said depleted lowermost first region.

49. A device according to claim 45, wherein said semiconductor material of said substrate is of said first conductivity type.