Split-level CMOS

• US 4,754,314 A
• Filed: 01/28/1987
• Issued: 06/28/1988
• Est. Priority Date: 01/24/1984
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Scott, David B., Malhi, Satwinder S.
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US07/009,004
• Time in Patent Office: 517 Days
• Field of Search: 357/42, 357/23.7, 357/59 E, 357/59 G, 357/59 K
• US Class Current: 257/70
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

A CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.

Claims

1. A CMOS integrated circuit, comprising:

(a) a single crystal semiconductor substrate;

(b) a field oxide defining a moat in said substrate;

(c) a continuous layer of semiconductor material contacting said substrate and extending over said field oxide, said layer forming a single crystal extension of said substrate in the regions contiguous thereto and forming a semiconductor device quality portion in the regions contiguous to said field oxide;

(d) an insulated gate field effect transistor formed in said extension of said substrate of a predetermined channel conductivity type;

(e) an insulated gate field effect transistor formed in said layer over said field oxide of the opposite channel conductivity type; and

(f) a source/drain region of one of said transistors being contiguous to a source/drain region of the other of said transistors.

2. A CMOS circuit as set forth in claim 1 wherein said predetermined channel conductivity type is N-type and said opposite channel conductivity type is P-type.

3. A CMOS circuit as set forth in claim 1 further including an insulating layer disposed over said transistors.

4. A CMOS circuit as set forth in claim 2 further including an insulating layer disposed over said transistors.

5. A CMOS circuit as set forth in claim 3 further including contact means extending through said insulating layer and contacting a said source/drain region thereunder.

6. A CMOS circuit as set forth in claim 4 further including contact means extending through said insulating layer and contacting a said source/drain region thereunder.