Dynamic ram having multiplexed twin I/O line pairs

• US 4,754,433 A
• Filed: 09/16/1986
• Issued: 06/28/1988
• Est. Priority Date: 09/16/1986
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chin, Daeje, Hwang, Wei, Lu, Nicky C.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US06/908,440
• Time in Patent Office: 651 Days
• Field of Search: 365/189, 365/203, 365/230, 365/233, 365/235
• US Class Current: 365/189.02
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

A dynamic random access memory (DRAM) is comprised of a first and a second input/output (I/O) bus, a first and a second I/O sense amplifier, and a first and a second I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal for enabling the operation of the I/O buses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per CAS cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O buses are alternately enabled, one being enabled when CAS is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.

Claims

1. A semiconductor memory device comprising circuitry operable for the storage and retrieval of data within said device, said device further comprising precharge means operable for periodically precharging at least a portion of said circuitry to a voltage potential, said circuitry being precharged being inoperable for the storage or retrieval of data therein during said precharging;

said device further comprising;

additional circuitry similarly operable for the storage and retrieval of data within said device;

additional precharge means operable for periodically precharging said additional circuitry to the voltage potential; and

control means responsive to one or more input control signals for selectively activating either said circuitry or said additional circuitry for storing and retrieving data while substantially simultaneously selectively activating the other one of said precharge means whereby the circuitry not activated for storing and retrieving data is precharged and whereby said device is provided at substantially all times with circuitry which is operable for the storage and retrieval of data.

2. A dynamic random access memory (DRAM) comprising:

a first input/output I/O bus coupling a first plurality of bit line sense amplifiers to a first I/O sense amplifier;

a second I/O bus coupling a second plurality of bit line sense amplifiers to a second I/O sense amplifier;

first precharge means for precharging said first I/O bus to a voltage potential;

second precharge means for precharging said second I/O bus to said voltage potential; and

control circuit means operable for enabling an individual one of said first or said second plurality of bit line sense amplifiers and a corresponding one of said first or said second I/O sense amplifiers, said circuit means simultaneously enabling the other one of said precharge means to precharge said associated bus.

3. The DRAM of claim 2 wherein said control circuit means is responsive to the states of at least a mode control signal, a column address strobe signal, a decoded column address signal and an address signal to enable said bit line sense amplifier, said I/O sense amplifier and said precharge means.

4. The DRAM of claim 2 wherein said control circuit means is responsive to the states of at least a mode control signal, a column address strobe signal and a decoded column address signal to enable said bit line sense amplifier, said I/O sense amplifier and said precharge means.

5. A dynamic random access memory (DRAM) responsive to a successive assertion and deassertion of a column address strobe signal for performing a page mode type of data transfer between a selected cell within a data storage array and a data bus, said DRAM comprising:

a first input/output (I/O) bus operable for coupling a first plurality of bit line sense amplifiers to a first input/output sense amplifier, each of said first plurality of bit line sense amplifiers being operatively coupled to a column of said cells, each of said bit line sense amplifiers further being couplable to said first I/O bust by an individual one of a first plurality of switching means;

a second I/O bus operable for coupling a second plurality of bit line sense amplifiers to a second I/O sense amplifier, each of said second plurality of bit line sense amplifiers being operatively coupled to a column of said cells, each of said bit line sense amplifiers further being couplable to said second I/O bus by an individual one of a second plurality of switching means;

first precharge means coupled to said first I/O bus for precharging said first I/O bus;

second precharge means coupled to said second I/O bus for precharging said second I/O bus; and

circuit means responsive to the state of each of at least a mode control signal, an address signal, and said column address strobe signal for selectively activating substantially simultaneously with one another either said first or said second precharge means, one of said switching means, and either said first or said second I/O sense amplifiers whereby one of said selected cells within said storage array is coupled to said data bus and whereby one of said first or said second I/O buses is precharged.

6. The DRAM of claim 5 wherein said circuit means has a first output state operable for selectively activating substantially simultaneously with one another said first I/O sense amplifier, one of said first plurality of switching means, and said second precharge means whereby said second I/O bus is precharged while said first I/O bus couples the selected one of said storage cells to said data bus;

and wherein said circuit means has a second output state for selectively activating substantially simultaneously with one another said second I/O sense amplifier, one of said second plurality of switching means, and said first precharge means whereby said first I/O bus is precharged while said second I/O bus couples the selected one of said storage cells to said data bus.

7. The DRAM of claim 6 wherein said circuit means is responsive to a first state of said mode control signal and an assertion of said column address strobe signal whereby the state of said address signal is determinative of whether said circuit means has said first output state or said second output state, said circuit means having said first or said second output state only during a time when said column address strobe signal is asserted.

8. The DRAM of claim 6 wherein said circuit means is responsive to a second state of said mode control signal whereby an assertion of said column address strobe signal causes said circuit means to have said first output state and, further, whereby a deassertion of said column address strobe signal causes said circuit means to have said second output state.

9. In a dynamic random access memory comprising an array of storage cells for storing data therein, said array having column bit lines associated therewith and bit line sense amplifiers coupled to said bit lines, said memory further comprising a first input/output (I/O) bus for coupling said bit line sense amplifiers to a first I/O sense amplifier, said first I/O sense amplifier further being coupled to a data bus whereby data may be transferred to or from said data bus and said storage cells, said memory further being comprised of a first I/O bus precharge means for precharging said first I/O bus in order that said first I/O bus is operable for transferring said data, the improvement comprising:

a second I/O bus coupled to said bit line sense amplifiers whereby equal numbers of said bit line sense amplifiers are coupled to each of said first and said second I/O buses;

a second I/O bus sense amplifier for coupling said second I/O bus to said data bus;

a second I/O bus precharge means for precharging said second I/O bus in order that said second I/O bus is operable for transferring data; and

control circuit means responsive to a control input for determining which of said first or said second I/O buses is to transfer data while simultaneously causing the precharging of the other one of said I/O buses.

10. A method of increasing the data transfer rate of a dynamic random access memory comprising the steps of:

providing a first input/output (I/O) bus for coupling a first plurality of bit line sense amplifiers to a first I/O sense amplifier;

providing a second I/O bus for coupling a second plurality of bit line sense amplifiers to a second I/O sense amplifier;

providing a first and a second precharge means for precharging the first and the second I/O buses, respectively; and

controlling the enabling of an individual one of the first or the second plurality of bit line sense amplifiers and a corresponding one of the first or the second I/O sense amplifiers while simultaneously controlling the enabling of the other one of the precharge means whereby an increased data transfer rate is achieved by substantially continuously providing for use one of the I/O buses.

11. The method of claim 10 wherein the step of controlling is accomplished by enabling the individual one of the first plurality of bit line sense amplifiers and the first I/O sense amplifier for transferring data while simultaneously precharging the second I/O bus during the time that a column address strobe signal is asserted and further, by enabling the individual one of the second plurality of bit line amplifiers and the second I/O sense amplifier for transferring data while simultaneously precharging the first I/O bus during the time that the column address strobe signal is deasserted.