Extremely lightweight, flexible semiconductor device arrays

• US 4,754,544 A
• Filed: 09/29/1986
• Issued: 07/05/1988
• Est. Priority Date: 01/30/1985
• Status: Expired due to Term

• Current Assignee: United Solar Systems Corp.
• Original Assignee: Energy Conversion Devices
• Inventors: Hanak, Joseph J.
• Primary Examiner(s): Weisstuch, Aaron
• Application Number:
  US06/913,046
• Time in Patent Office: 645 Days
• Field of Search: 29/572, 29/577 R, 29/580, 29/588, 29/590, 29/591, 136/251, 136/244, 136/249 MS, 136/258 AM
• US Class Current: 438/66
• CPC Class Codes: H01L 31/03921 including only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/046 PV modules composed of a plurality of thin film solar cells deposited on the same substrate
• CPC Class Codes: H01L 31/0463 characterised by special patterning methods to connect the PV cells in a module, e.g. laser cutting of the conductive or active layers
• CPC Class Codes: H01L 31/0465 comprising particular structures for the electrical interconnection of adjacent PV cells in the module H01L31/0463 takes precedence
• CPC Class Codes: H01L 31/048 Encapsulation of modules
• CPC Class Codes: H01L 31/206 Particular processes or apparatus for continuous treatment of the devices, e.g. roll-to roll processes, multi-chamber deposition
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10S 438/928 Front and rear surface processing

Abstract

An extremely lightweight, interconnected array of semiconductor devices, such as solar cells, is formed from a large continuous area of semiconductor material disposed on an unconventionally thin, electrically conducting substrate. The interconnections are formed by removing portions of the substrate to form substrate islands underlying a layer of semiconductor material which underlies a transparent conductive oxide. The oxide layer may likewise be formed into mutually isolated islands that overlay the areas between the substrate islands. Individual units or cells so formed may be interconnected by depositing a conducting material on, alongside and at least partially between islands of oxide and/or semiconductor, by depositing a metal grid on the oxide layer and burning conducting paths to the substrate islands, or by piercing the layers and disposing a conducting material in the holes pierced.

The unconventionally thin substrate may be a sheet of electroformed nickel or other thin metal or an initially thick substrate that is thinned by chemical etching after other array processing steps are completed. An encapsulant is preferably applied to the exposed surface of the semiconducting material to protect it while the substrate is being thinned or removed. Subsequently, an encapsulant is applied to the rear of substrate side of the array.

Claims

1. A process for producing an electronic device, said process including the steps of:

providing a substrate member;

depositing a semiconductor body atop the substrate;

subjecting the semiconductor body bearing side of the device to further processing steps;

encapsulating the semiconductor body bearing side;

subjecting the substrate side of the device to further processing steps; and

encapsulating the substrate side of the device.

2. A process as in claim 1, wherein the step of subjecting the semiconductor body bearing bearing side of the device to further processing includes depositing an electrically conductive coating on the semiconductor material.

3. A process as in claim 2, wherein the step of depositing an electrically conductive coating comprises selecting said coating from the group consisting essentially of:

indium tin oxide, cadmium tin oxide, antimony tin oxide, and combinations thereof.

4. A process as in claim 2, wherein the step of subjecting the semiconductor body bearing side of the device to further processing includes the further step of selectively removing a portion of the semiconductor body and the conductive coating so as to form a plurality of islands of semiconductor material on the substrate.

5. A process as in claim 4, including the further step of providing an electrical connection between the conductive layer of at least one of said plurality of islands and the substrate.

6. A process as in claim 1, wherein the step of subjecting the semiconductor body bearing side of the device to further processing includes patterning the semiconductor body.

7. A process as in claim 1, wherein the step of subjecting the substrate side of the device to further processing includes etching the substrate.

8. A process as in claim 7, wherein the step of etching the substrate comprises reducing the thickness of the substrate to less than 25 micrometers.

9. A process as in claim 7, wherein the step of etching the substrate comprises removing portions of the substrate so as to create a plurality of islands thereof.

10. A process as in claim 1, wherein the step of subjecting the substrate side of the device to further processing includes the step of establishing electrical communication to the substrate.