Manufacturing method of insulated gate field effect transistor using reflowable sidewall spacers

• US 4,755,479 A
• Filed: 02/04/1987
• Issued: 07/05/1988
• Est. Priority Date: 02/17/1986
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Miura, Takao
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/010,667
• Time in Patent Office: 517 Days
• Field of Search: 29/571, 29/576 B, 29/576 W, 29/577 C, 29/578, 29/591, 148/187, 148/DIG. 42, 148/35, 148/44, 148/51, 148/53, 148/76, 148/82, 148/83, 148/106, 148/133, 148/145, 148/157, 148/161, 156/643, 156/646, 156/662, 357/23.3, 357/23.12, 357/68, 357/71, 357/54, 427/93, 437/44
• US Class Current: 438/303
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66598 forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: Y10S 148/044 Edge diffusion under mask
• CPC Class Codes: Y10S 148/106 Masks, special
• CPC Class Codes: Y10S 148/157 Special diffusion and profiles
• CPC Class Codes: Y10S 148/161 Tapered edges
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer
• CPC Class Codes: Y10S 257/919 Elements of similar construction connected in series or parallel to average out manufacturing variations in characteristics
• CPC Class Codes: Y10S 438/965 Shaped junction formation

Abstract

With an increase of integration density in an integrated circuit, the channel length of MIS FET becomes shorter and shorter, which causes a hot carrier effect. To solve the problem, the doping profile of source/drain regions and doping amount must be precisely controlled such that a strong electric field is not generated in a transition region from channel to drain. To obtain this objective, the present invention discloses a method, in which reflowed sidewalls of doped silicate glass having a gentle slope are formed on both sides of a gate electrode, and the gate electrode and the sidewalls thus formed are used as a mask for ion implantation. The depth of ion implantation and the doping amount change gradually from the channel region to the drain region avoiding a generation of the strong electric field and thus alleviates the short channel trouble. The present invention has also an effect of obtaining a passivation layer having gentle slope on the surface and avoiding a broken wire trouble of aluminum wiring.

Claims

1. A method of manufacturing MIS FET, said method comprising the steps of:

(a) forming a gate insulating film and a gate electrode on a silicon substrate;

(b) depositing an insulating material on said substrate and said gate electrode;

(c) reflowing said insulating material;

(d) etching said reflowed insulating material until the surface of said gate electrode and substrate for source/drain regions are exposed, thereby making a gradually rising side wall of said reflowed insulating material remain on both sides of the gate electrode; and

(e) implanting impurity ions into said substrate to form source/drain regions of said MIS FET using said gate electrode and said side walls as a mask, whereby a doping zone having a slanted profile which becomes gradually shallower under an edge of said gate electrode is formed.

3. A method of manufacturing MIS FET according to claims 1 or 2, wherein said insulating material is a doped silicate glass having a reflow temperature below 1100°

C.

4. A method of manufacturing MIS FET according to claim 3, wherein said silicate glass is doped with an oxide of phosphorus (P) or boron (B) or arsenic (As), or a combination thereof.

5. A method of manufacturing MIS FET according to claim 1, wherein said etching step is performed until the surface of said gate electrode is exposed and the surface edge thereof is partly removed, forming a continuous curved surface together with said side wall.

2. A method of manufacturing MIS FET, said method comprising the steps of:

(a) forming a gate insulating film and a gate electrode on a silicon substrate;

(b) depositing an insulating material on said substrate and said gate electrode;

(c) etching said insulating material until the surface of said gate electrode and substrate for source/drain regions are exposed, thereby making a side wall of said insulating material remain on both sides of said gate electrode;

(d) reflowing the remaining insulating material, whereby a gradually rising side wall of said insulating material are formed on both sides of the gate electrode; and

(e) implanting impurity ions into said substrate to form source/drain regions of said MIS FET using said gate electrode and said side walls as a mask, whereby a doping zone having a slanted profile which gradually becomes shallower under an edge of said gate electrode is formed.