Housing for encapsulating an electronic circuit

• US 4,755,910 A
• Filed: 12/17/1986
• Issued: 07/05/1988
• Est. Priority Date: 12/17/1985
• Status: Expired due to Fees

• Current Assignee: Cimsa Sintra
• Original Assignee: Cimsa Sintra
• Inventors: Val, Christian
• Primary Examiner(s): TOLIN, GERALD P
• Application Number:
  US06/942,655
• Time in Patent Office: 566 Days
• Field of Search: 339/17 CF, 361/321, 361/321 C, 361/386, 361/388, 361/395, 361/399, 361/400, 361/401, 361/403, 361/412, 361/413, 361/414, 357/68, 357/71, 357/74, 357/80, 357/81, 174/52 FP, 439/55, 439/68, 439/70, 439/69, 439/76
• US Class Current: 361/763
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/206 : Length ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10S 257/916 : Narrow band gap semiconductor material, <<1ev

Abstract

A housing more particularly intended for encapsulating a wafer scale electronic circuit, realized in hybrid technology or integrated on semi-conducting substrate. In this housing:

supply voltages are brought to different points disposed over the surface of the circuit

lead-in circuits are constituted by conducting planes, placed in superimposed layers in the cover or the base of the housing.

Claims

1. A housing encapsulating an integrated circuit, comprising a base on which is disposed said circuit and a cover mounted over said base and closing the housing, wherein said circuit is provided with a plurality of studs and at least one centrally located opening, said studs divided into two groups, a first group positioned at the periphery of said circuit and a second group positioned at the periphery of said opening, said studs receiving supply voltages for said circuit, said housing comprising means for connecting said supply voltages to said studs of the circuit, said connecting means comprising at least one conducting plane, for each supply voltage positioned in superimposed layers, without electrical contact between one another, within said cover and/or said base.

2. A housing according to claim 1, wherein the planes form a capacitance.

3. A housing according to claim 1, wherein said integrated circuit is a hybrid circuit.

4. A housing according to claim 3, wherein said hybrid circuit is divided into a plurality of parts.

5. A housing according to claim 1, wherein said circuit is provided with a central opening, said housing further comprising a central pillar, secured to said base and passing through said opening of said circuit, said cover resting on said base and said central pillar.

6. A housing according to claim 1, wherein said base includes a bottom, on which is disposed said circuit and an annular structure, secured to the periphery of said bottom and supporting said cover.

7. A housing according to claim 6, wherein said bottom supports said central pillar.

8. A housing according to claim 1, wherein said circuit is provided with a plurality of openings said studs being positioned at the periphery of said circuit and around said openings.

9. A housing according to claim 1, wherein said base further forms a thermal drain.

10. A housing according to claim 1, further comprising a second circuit disposed on another face of said base, said second circuit receiving a second cover, thus encapsulating said second circuit.