Process for preparing a silicon carbide device

• US 4,757,028 A
• Filed: 10/02/1986
• Issued: 07/12/1988
• Est. Priority Date: 10/07/1985
• Status: Expired due to Fees

• Current Assignee: Agency of Industrial Science & Technology (Government of Japan)
• Original Assignee: Agency of Industrial Science & Technology (Government of Japan)
• Inventors: Takahashi, Tatsuo, Kondoh, Yasushi, Hayashi, Yutaka
• Primary Examiner(s): Chaudhuri, Olik
• Application Number:
  US06/914,498
• Time in Patent Office: 649 Days
• Field of Search: 357/61, 148/DIG. 148, 148/DIG. 147, 437/40, 437/100, 437/233, 437/192, 437/193, 437/238, 437/239, 437/241, 437/242, 437/255
• US Class Current: 438/571
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: Y10S 148/148 Silicon carbide
• CPC Class Codes: Y10S 438/931 Silicon carbide semiconductor

Abstract

A silicon carbide layer(s) is provided on a silicon substrate. If necessary, a desired pattern of the silicon carbide layer(s) is allowed to remain, while the other portion(s) is embedded with SiO₂. If necessary, the silicon carbide layer(s) may be constituted of a barrier layer and a device-forming layer. A layer capable of easily forming an insulating layer, such as a polycrystalline silicon layer, is provided on the silicon carbide layer to form first electrodes, followed by insulation of the surface, such as oxidation of the surfaces of the first electrodes and the silicon carbide layer. Second electrodes are further formed in self alignment by utilizing the insulating layer of the surface of the first electrodes. This process is useful in preparation of a silicon carbide device capable of operation at high temperatures.

Claims

1. A process for preparing a field effect transistor of silicon carbide, comprising the steps of:

(a) depositing a first electrically conductive layer on the surface of a silicon carbide layer;

(b) partially removing said first electrically conductive layer and exposing a surface of said silicon carbide layer to obtain two spaced apart regions of said first electrically conductive layer, said two spaced apart regions of the first electrically conductive layer constituting a source and a drain electrode of a field effect transistor of silicon carbide to be prepared, the space between said source electrode and said drain electrode defining in said silicon carbide layer a channel region of said field effect transistor;

(c) forming insulating layers on surfaces of said source electrode, said drain electrode, and said exposed silicon carbide layer, wherein, owing to the differences in the formation rates of said insulating layers, said insulating layers on said exposed silicon carbide layer are thinner than those on said source and drain electrodes;

(d) depositing a second electrically conductive layer on said insulating layers; and

(e) partially removing said second electrically conductive layer in a pattern which leaves portions thereof remaining at least above said channel region to provide a gate electrode of said field effect transistor, said gate electrode being insulated from said source and said drain by said insulating layers.

2. The process for preparing a field effect transistor of silicon carbide of claim 1, wherein the method of forming said insulating layers is oxidation in an oxidizing gas atmosphere.

3. The process for preparing a field effect transistor of silicon carbide of claim 1, wherein the method of forming said insulating layers is nitridation in an nitridizing gas atmosphere.

4. The process for preparing a field effect transistor of silicon carbide of claim 1, wherein said first electrically conductive layer is polycrystalline silicon.

5. The process for preparing a field effect transistor of silicon carbide of claim 1, wherein said first electrically conductive layer is a silicide, and wherein said step (c) forms said insulating layers at a higher rate over said silicide than over said silicon carbide.

6. The process for preparing a field effect transistor of silicon carbide of claim 1, wherein said first electrically conductive layer comprises a metal selected from the group consisting of tantalum and titanium.

7. The process for preparing a field effect transistor of silicon carbide of claim 1, wherein said first electrically conductive layer has ohmic contact with said silicon carbide layer.

8. The process for preparing a field effect transistor of silicon carbide of claim 1, wherein said first electrically conductive layer has rectifying contact with said silicon carbide layer.

9. A process for preparing a field effect transistor of silicon carbide, comprising the steps of:

depositing a first electrically conductive layer on the surface of a silicon carbide layer;

dividing said first electrically conductive layer into two portions by partially removing said first conductive layer and exposing a surface of said silicon carbide layer, said two portions of first electrically conductive layer constituting a source and a drain electrode of a field effect transistor of silicon carbide to be prepared, the space between said source electrode and said drain electrode defining in said silicon carbide layer a channel region of said field effect transistor;

forming insulating layers on surfaces of said source electrode, said drain electrode, and said exposed silicon carbide layer, wherein, owing to the differences in the formation rates of said insulating layers, said insulating layers on said exposed silicon caribde layer are thinner than those on said source and drain electrodes;

removing said insulating layer only on said exposed silicon carbide layer to expose said silicon carbide layer again;

depositing a second electrically conductive layer on said insulating layers, wherein second electrically conductive layer has rectifying contact with said silicon carbide layer; and

partially removing said second electrically conductive layer in a pattern which leaves portions thereof remaining at least above said channel region to provide a gate electrode of said field effect transistor which is insulated from said source electrode and said drain electrode by said insulating layers.