Apparatus for estimating the square root of digital samples

• US 4,757,467 A
• Filed: 05/15/1986
• Issued: 07/12/1988
• Est. Priority Date: 05/15/1986
• Status: Expired due to Fees

• Current Assignee: RCA Corporation
• Original Assignee: RCA Licensing Corporation
• Inventors: Dieterich, Charles B., Christopher, Todd J.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Shaw, Dale M.
• Application Number:
  US06/863,431
• Time in Patent Office: 789 Days
• Field of Search: 364/752
• US Class Current: 708/605
• CPC Class Codes: G06F 7/5525 Roots or inverse roots of single operands

Abstract

Circuitry for calculating the square root of a binary number iterates the equation E(K+1)=E(K)+(S-E(K)²) where E(K+1) is the current estimate of the square root of the sample S and E(K) is the previous estimate. The value E(K)² is estimated in order to reduce the complexity of the hardware. An application is described for real time processing of digital audio signals in serial-bit format.

Claims

1. Apparatus for calculating the square roots of binary samples, comprising:

a signal input terminal for supplying said binary samples;

storage means having an input terminal and an output terminal, for storing samples therein;

sample combining means having a first input terminal coupled to the output terminal of said storage means, an output terminal coupled to the input terminal of said storage means and having a second input terminal;

squaring means coupled to the output terminal of said storage means for generating samples having values representing the squares of samples coupled thereto, and having an output terminal;

sample differencing means having first and second input terminals coupled to said signal input terminal and to the output terminal of said squaring means, respectively, and having an output terminal; and

means for coupling the output terminal of said sample differencing means to the second input terminal of said signal combining means; and

wherein values representing the square roots of said binary samples are provided at the output terminal of said sample combining means.

2. The apparatus set forth in claim 1 wherein said means for coupling includes:

means coupled between said sample combining means and said sample differencing means and having a control input terminal, for changing the bit significance of samples applied thereto responsive to a control signal;

means coupled to said signal input terminal for generating said control signals representing the characteristics of the logarithm (base

     2) of said binary samples; and

means for coupling said control signals to said control input terminal.

3. The apparatus set forth in claim 2 wherein said bit significance changing means effects a multiplication of samples applied thereto by a factor 2 exp[-INT(log₄ (S_R)] where S_R is the value of respective binary samples applied to said signal input terminal, and INT denotes the integer part of log₄ (S_R).

4. The apparatus set forth in claim 1 wherein said means for coupling includes:

means coupled between said sample combining means and said sample differencing means and having a control input terminal, for changing the bit significance of samples applied thereto responsive to a control signal;

means coupled to the output terminal of said sample combining means for generating said control signals, representing the characteristic of the logarithm (base

     2) of samples produced from said combining means; and

means for coupling said control signals to said control input terminal.

5. The apparatus set forth in claim 1 wherein such apparatus processes N-bit serial-bit binary samples (N being an integer) and said storage means comprises:

serial-bit shift register means arranged to load samples bit-seriatum and to segment N-bit samples into L least significant bits (LSB'"'"'s) and (N-L) most significant bits (MSB'"'"'s) (L being an integer), said shift register mean having provision for outputting in parallel the (N-L) MSB'"'"'s of the N-bit samples and having a serial-bit output terminal for outputting the N-bit samples bit-seriatum.

6. The apparatus set forth in claim 5 wherein the squaring means comprises:

a serial-parallel multiplier having a parallel-bit input port and a serial-bit input port, and having an output port coupled to said sample differencing means;

means for coupling said (N-L)-MSB'"'"'s from said storage means to said parallel-bit input port; and

means for coupling the serial-bit input port of the serial-parallel multiplier to the serial-bit output terminal of the shift register means.

7. The apparatus set forth in claim 6 wherein the means for coupling the output terminal of said sample differencing means to the second input terminal of said signal combining means includes a serial shift register having input and output terminals coupled to said differencing and combining means respectively.

8. The apparatus set forth in claim 7 wherein said serial shift register coupled between the differencing and combining means further includes a control signal input port and said serial shift register provides a variable delay period responsive to control signals applied to said control signal input port.

9. The apparatus set forth in claim 8 wherein the means for coupling the output terminal of said sample differencing means to said sample combining means further includes:

means, coupled to said signal input terminal for applying binary samples, for generating a signal representing the characteristic part of the logarithm (base

     2) of said binary samples; and

means, coupled to said means for generating said characteristic part for generating said control signals to control the delay period of said serial shift register.

10. The apparatus set forth in claim 8 wherein the means for coupling the output terminal of said sample differencing means to said sample combining means further includes:

means, coupled to the output terminal of said sample combining means, for generating a signal representing the characteristic part of the logarithm (base

     2) of said binary samples; and

means, coupled to said means for generating said characteristic part, for generating said control signals to control the delay period of said serial shift register.

11. Apparatus for estimating the square root of a binary sample comprising:

a sample input terminal for applying said binary sample;

storage means having an input and an output terminal, for storing a sample corresponding to an estimate of the square root of said binary sample;

sample squaring means, having an output terminal, an input terminal coupled to the output terminal of said storage means, for generating samples representing the squares of estimates provided by said storage means;

sample combining means coupled to said sample input terminal and respective output terminals of said storage and squaring means for combining said estimate, the square of said estimate and said binary sample in the ratio 2;

-1;

1;

means for coupling combined samples from said combining means to the input terminal of said storage means; and

wherein estimates of the square root of said binary sample are provided at the output terminal of said sample combining means and at the output terminal of said storage means.