Authenticated read-only memory

• US 4,757,468 A
• Filed: 04/21/1987
• Issued: 07/12/1988
• Est. Priority Date: 09/22/1982
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Nguyen, Tai, Shirgley, David A., Domenik, Stephen L., Folmsbee, Alan C.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US07/040,860
• Time in Patent Office: 448 Days
• Field of Search: 235/382, 364/200 MS File, 364/900 MS File, 340/825.3, 340/825.31, 340/825.32, 340/825.34, 380/4, 380/47, 380/50
• US Class Current: 713/193
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 7/584 using finite field arithmetic, e.g. using a linear feedback shift register
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

An apparatus for controlling access to a program stored in a read-only memory is described. In one embodiment, the memory includes a random number generator and an encryptor for encrypting random numbers from the generator. A second encryptor which provides identical encryption to the first encryptor is included within the system and is coupled to receive random numbers from the generator. A comparator compares the results from the first and second encryptors and if they are identical, enables the memory. The encryptors are programmable with a 64-bit key and 32-bit random numbers are used. By making the encryption process relatively slow (e.g., one second) many decades are required to break the key.

Claims

1. An apparatus for controlling access to a memory comprising:

generator means for generating random digital signals;

first encryption means for providing first predetermined encryption for digital signals, said first encryption means including an accumulator, a key shift register, a wire crossing means, a read-only-memory (ROM) and a data latch, said first encryption means coupled to said generator means;

said wire crossing means coupled to said accumulator and said key shift register for providing a permutation code for providing said first encryption;

second encryption means for providing second predetermined encryption for digital signals, said second encryption means coupled to said generator means;

comparator means for comparing two digital signals, said comparator means coupled to said first and second encryption means for receiving said encryped signals, said comparator means coupled to said memory for enabling access to said memory as a function of said comparison,

said first encryption means receiving said random digital signals from said generator means and loading said signals into said accumulator;

said key shift register loading a key which is stored in said memory;

a first group of bits from said accumulator being coupled to said wire crossing means and crossed in accordance with a function determined by first key bits stored in said key shift register and coupled as an output of said wire crossing means which is then exclusively OR'"'"'ed with second key bits stored in said key shift register and outputted;

said exclusively OR'"'"'ed output being coupled to said ROM to access coded data stored in said ROM which data is then loaded into said latch;

said random digital signal in said accumulator being shifted a predetermined number of bits and a second group of bits being exclusively OR'"'"'ed with said data in said latch and shifted into said accumulator to perform a permutation within said accumulator;

whereby access to said memory is controlled as a function of the encryped signals from said first and second encryption means.

2. The apparatus defined by claim 1 wherein said first predetermined encryption is the same as said second predetermined encryption, and wherein said comparator means enables said access to said memory if said signals from said first and second encryption means are the same.

3. The apparatus defined by claim 2 wherein said memory is a first read-only memory and wherein said generator means, first encryption means and comparator means are integrated within a same physical unit containing said first memory.

4. The apparatus defined by claim 3 wherein said second encryption means is integrated within the same physical unit containing a second read-only memory.

5. An apparatus for controlling access to a memory comprising:

generator means for generating random digital signals;

first encryption means for providing first predetermined encryption for digital signals, said first encryption means including an accumulator, a key shift register, a wire crossing means, a read-only-memory (ROM) and a data latch, said generator means for receiving said random signals from said generator means;

said wire crossing means coupled to said accumulator and said key shift register for providing a permutation code for providing said first encryption;

second encryption means for providing second predetermined encryption for digital signals, said second encryption means being coupled to receive encrypted signals from said first encryption means;

comparator means for comparing two digital signals, said comparator means coupled to receive said random signals form said generator means and encrypted signals from said second encryption means, said comparator means coupled to said memory for enabling said memory as a function of said comparison,

said first encryption means receiving said random digital signals from said generator means and loading said signals into said accumulator;

said key shift register loading a key which is stored in said memory;

a first group of bits from said accumulator being coupled to said wire crossing means and crossed in accordance with a function determined by first key bits stored in said key shift register and coupled as an output of said wire crossing means which is then exclusively OR'"'"'ed with second key bits stored in said key shift register and outputted;

said exclusively OR'"'"'ed output being coupled to said ROM to access coded data stored in said ROM which data is then loaded into said latch;

said random digital signal in said accumulator being shifted a predetermined number of bits and a second group of bits being exclusively OR'"'"'ed with said data in said latch and shifted into said accumulator to perform a permutation within said accumulator;

whereby access to said memory is controlled and access is permitted only when said first and second encryption means are present and perform said first and second predetermined encryption.

6. The apparatus defined by claim 5 wherein said second predetermined encryption performs the inverse encryption to said first predetermined encryption.

7. The apparatus defined by claim 6 wherein said comparator means enables access to said memory if said random signals from said generator means are the same as said encrypted signals from said second encryption means.

8. In a computer system wherein a program for said computer system is stored in a first memory, an apparatus for permitting only authenticated access to said program comprising:

a first programmable encryption means for encrypting a digital number in accordance with a programmed key, said first encryption means being integrated within the same physical unit containing said first memory, said first encryption means including an accumulator, a key shift register, a wire crossing means, a read-only-memory (ROM) and a data latch;

said wire crossing means coupled to said accumulator, and said key shift register for providing a permutation code for providing said first encryption;

a random number generator for generating digital number, said random number generator being integral with said first memory and being coupled to said first encryption means;

a comparator, said comparator being integral with said first memory and being coupled to said first encryption means;

a second programmable encryption means for encrypting a digital number in accordance with a programmed key, said second encryption means being coupled to said computer system and being coupled to said random number generator and said comparator means;

said comparator means being coupled to said first memory to enable access to said first memory if said first and second encryption means are programmed with the same key;

said first encryption means receiving said random digital signals from said random number generator and loading said signals into said accumulator;

said key shift register loading a key which is stored in said memory;

a first group of bits from said accumulator being coupled to said wire crossing means and crossed in accordance with a function determined by first key bits stored in said key shift register and coupled as an output of said wire crossing means which is then exclusively OR'"'"'ed with second key bits stored in said key shift register and outputted;

said exclusively OR'"'"'ed output being coupled to said ROM to access coded data stored in said ROM which data is then loaded into said latch;

said random digital signal in said accumulator being shifted a predetermined number of bits and a second group of bits being exclusively OR'"'"'ed with said data in said latch and shifted into said accumulator to perform a permutation within said accumulator;

whereby access to said program stored in said first memory is controlled as a function of said first encryption means and said second encryption means.

9. The apparatus defined by claim 8 wherein said first memory is an electrically programmable read-only memory and wherein said second encryption means is a second electrically programmable read-only memory.

10. The apparatus defined by claim 9 wherein said first encryption means and second encryption means are identical.

11. An apparatus for controlling access to a memory comprising:

a random signal generator for generating random digital signals;

a first encryptor coupled to said random signal generator for providing first predetermined encryption of said random digital;

signals;

said first encryptor including an accumulator, a key shift register, a wire crossing means, a read-only-memory (ROM) and a data latch;

said wire crossing means coupled to said accumulator and said key shift register for providing a permutation code to provide said first predetermined encryption;

a second encryptor coupled to said random signal generator for providing second predetermined encryption of said random digital signals;

a comparator coupled to said first and second encryptor for comparing said first and second encryptions;

said comparator also coupled to said memory for enabling access to said memory when said comparison is an expected result;

said first encryptor, random signal generator and comparator are fabricated in a same semiconductor ship as said memory;

said first encryption means receiving said random digital signals from said random number generator and loading said signals into said accumulator;

said key shift register loading a key which is stored in said memory;

a first group of bits from said accumulator being coupled to said wire crossing means and crossed in accordance with a function determined by first key bits stored in said key shift register and coupled as an output of said wire crossing means which is then exclusively OR'"'"'ed with second key bits stored in said key shift register and outputted;

said exclusively OR'"'"'ed output being coupled to said ROM to access coded data stored in said ROM which data is then loaded into said latch;

said random digital signal in said accumulator being shifted a predetermined number of bits and a second group of bits being exclusively OR'"'"'ed with said data in said latch and shifted into said accumulator and repeating said exclusive OR'"'"'ing and shifting into said accumulator operation a predetermined number of times and then performing a permutation within said accumulator;

shifting said key stored in said key shift register, and repeating sequence of encryption;

whereby access to said memory is controlled as a function of said comparison of said encryptions from said first and second encryptions.

12. The apparatus defined by claim 11 wherein when said first predetermined encryption is the same as said second predetermined encryption, said comparator enables said access to said memory.

13. The apparatus defined by claim 12 wherein said semiconductor chip is fabricated using EPROM technology.

14. An apparatus for controlling access to a memory comprising:

a random signal generator for generating random digital signals;

a first encryptor coupled to said random signal generator for providing first predetermined encryption of said random digital signals;

a second encryptor coupled to said first encryptor for encrypting said first predetermined encryption and providing a second predetermined encryption;

said first and second encryptors each including an accumulator, a key shift register, a wire crossing means, read-only-memory (ROM) and a data latch, wherein said wire crossing means is coupled to its respective accumulator and said key shift register for providing its respective permutation code for its respective encryption;

a comparator coupled to said random signal generator and said second encryptor for comparing said second encryption to said random digital signal;

said comparator also coupled to said memory for enabling access to said memory when said comparison is an expected result;

said first encryptor, random signal generator and comparator are fabricated in a same semiconductor chip as said memory,

said first encryption means receiving said random digital signals from said random number generator and loading said signals into said accumulator;

said key shift register loading a key which is stored in said memory;

a first group of bits from said accumulator being coupled to said wire crossing means and crossed in accordance with a function determined by first key bits stored in said key shift register and coupled as an output of said wire crossing means which is then exclusively OR'"'"'ed with second key bits stored in said key shift register and outputted;

said exclusively OR'"'"'ed output being coupled to said ROM to access coded data stored in said ROM which data is then loaded into said latch;

said random digital signal in said accumulator being shifted a predetermined number of bits and a second group of bits being exclusively OR'"'"'ed with said data in said latch and shifted into said accumulator and repeating said exclusive OR'"'"'ing and shifting into said accumulator operation a predetermined number of times and then performing a permutation within said accumulator;

shifting said key stored in said key shift register, and repeating sequence of encryption;

said second encryption functioning equivalently to said first encryption means;

whereby access to said memory is controlled as a function of said comparison of said comparator;

15. The apparatus as defined in claim 14, wherein when said second encryption is the same as said random digital signal, said comparator enables said access to said memory.

16. The apparatus defined by claim 15 wherein said semiconductor chip is fabricated using EPROM technology.