Memory circuit
First Claim
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1. A memory circuit comprising:
- a memory cell array including means for reading out data bits contained in a row of the array in parallel;
a data latch circuit for holding the read data bits;
a signal line for applying a control signal to indicate one of two modes to said data latch circuit; and
a control circuit connected to said signal line for causing said data latch circuit to selectively output a plurality of said data bits in parallel when said control signal incidates a first mode and for causing said data latch circuit to selectively output said plurality of data bits serially one bit at a time when said control signal indicates a second mode.
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Abstract
A dual-port memory circuit comprises a random port having a memory cell array randomly accessable and a serial port serially readable or writable from/to the memory cell array. In the memory circuit, two modes are provided to the serial port, and when a first mode is designated, the data are consecutively read or written a plurality of bits at a time, and when a second mode is designated, the data are consecutively read or written one bit at a time. High speed read/write operation is attained by designating the mode to allow parallel input/output. For an application which does not require high speed operation, the number of components to be externally added to the memory circuit can be reduced.
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Citations
7 Claims
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1. A memory circuit comprising:
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a memory cell array including means for reading out data bits contained in a row of the array in parallel; a data latch circuit for holding the read data bits; a signal line for applying a control signal to indicate one of two modes to said data latch circuit; and a control circuit connected to said signal line for causing said data latch circuit to selectively output a plurality of said data bits in parallel when said control signal incidates a first mode and for causing said data latch circuit to selectively output said plurality of data bits serially one bit at a time when said control signal indicates a second mode. - View Dependent Claims (2, 3)
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4. A memory circuit comprising:
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a memory cell array including means for reading out data bits controlled in a row of the array in parallel; a data latch circuit for holding the data bits to be written into said memory cell array; a signal line for applying a signal to indicate one of first and second modes to said data latch circuit; and a control circuit connected to said signal line for selecting a plurality of data bits to be supplied in parallel to said data latch circuit when said signal line indicates the first mode and for selecting data bits to be supplied serially bit by bit to said data latch circuit when said signal line indicates the second mode. - View Dependent Claims (5, 6)
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7. A memory circuit comprising:
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a memory cell array including means for reading out data bits contained in a row of the array in parallel; a data latch circuit for holding data bits to be read-out from said memory cell array; a signal line for applying a control signal to indicate one of first and second modes and a control circuit connected to said signal line for selecting a plurality of data bits to be outputted in parallel from said data latch circuit when said control signal indicates the first mode and the selecting the data bits to be outputted serially bit by bit from said data latch circuit when said control signal indicates the second mode.
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Specification