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Memory circuit

  • US 4,757,473 A
  • Filed: 05/21/1986
  • Issued: 07/12/1988
  • Est. Priority Date: 05/22/1985
  • Status: Expired due to Fees
First Claim
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1. A memory circuit comprising:

  • a memory cell array including means for reading out data bits contained in a row of the array in parallel;

    a data latch circuit for holding the read data bits;

    a signal line for applying a control signal to indicate one of two modes to said data latch circuit; and

    a control circuit connected to said signal line for causing said data latch circuit to selectively output a plurality of said data bits in parallel when said control signal incidates a first mode and for causing said data latch circuit to selectively output said plurality of data bits serially one bit at a time when said control signal indicates a second mode.

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