Semiconductor memory device having redundancy circuit portion

• US 4,757,474 A
• Filed: 01/21/1987
• Issued: 07/12/1988
• Est. Priority Date: 01/28/1986
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Maki, Yasuhiko, Fukushi, Isao
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/011,268
• Time in Patent Office: 538 Days
• Field of Search: 365/189, 365/182, 365/230, 365/207, 365/210
• US Class Current: 365/189.07
• CPC Class Codes: G11C 29/806 by reducing size of decoders

Abstract

A semiconductor memory device includes a redundancy circuit having upper address bit input terminals receiving upper address bit, lower address bit input terminals receiving lower address bits, a regular memory cell array having a plurality of word lines and bit lines, and a plurality of memory cells are arranged at each intersection of the word and bit lines. A redundancy memory cell array is provided having a plurality of word and bit lines, and a plurality of memory cells are arranged at each intersection of the word and bit lines. The capacity of the redundancy memory cell array being smaller than the regular memory cell array. A first selection circuit selects a word or bit line in the regular memory cell array in accordance with the upper and lower address bits. A second selection circuit select a word or bit line in the redundancy memory cell array in accordance with the lower address bits. A redundancy address programming circuit programs the upper address bits corresponding to defective memory cells in the regular memory cell array. A control circuit compares the input upper address bits with the programmed upper address bits and controls the first and second selection circuits to inhibit the selection of the word or bit lines in the regular memory cell array. A predetermined word or bit line in the redundancy memory cell array is selected therefor when each of the input upper address bits coincides with each of the programmed upper address bits.

Claims

1. A semiconductor memory device comprising:

one or more upper address bit input terminals connected to receive one or more upper address bits;

one or more lower address bit input terminals connected to receive one or more lower address bits;

a regular memory cell array including;

a plurality of word lines;

a plurality of bit lines intersecting said word lines; and

a plurality of memory cells arranged at the intersections of said word lines and bit lines and including a defective memory cell;

a redundancy memory cell array including;

a plurality of word lines;

a plurality of bit lines intersecting said word lines; and

a plurality of memory cells arranged at the intersections of said word lines and bit lines, the capacity of said redundancy memory cell array being less than the capacity of said regular memory cell array;

first selection means, connected to said upper and lower address bit input terminals and to said regular memory cell array, for selecting one of said word lines and bit lines in said regular memory cell array in accordance with said upper address bits and lower address bits;

second selection means, connected to said lower address bit input terminals and to said redundancy memory cell array, for selecting one of said word lines and bit lines in said redundancy memory cell array in accordance with said lower address bits;

redundancy address programming means, connected to said regular memory cell array, for programming one or more upper address bits of address data corresponding to the defective memory cell in said regular memory cell array; and

control means, connected to said regular memory cell array and said redundancy memory cell array, for comparing each of said input upper address bits with each of said programmed upper address bits and for controlling said first and second selection means so that the selection of one of said word lines and bit lines in said regular memory cell array is inhibited and a predetermined one of said word lines and bit lines in said redundancy memory cell array is selected instead, when each of said input upper address bits coincides with each of said programmed upper address bits.

2. A semiconductor memory device according to claim 1, wherein said first selection means comprises:

first prestage decoder means, coupled to receive said input upper address bits, for decoding said input upper address bits and outputting an output signal;

second prestage decoder means, coupled to receive said input lower address bits, for decoding said input lower address bits and outputting an output signal; and

poststage decoder means, coupled to said first and second prestage decoder means, for receiving and decoding the output signals from said first and second prestage decoder means; and

wherein

said second selection means comprises;

a circuit, coupled to said first selection means, for receiving the output signal from said second prestage decoder means and for selecting a predetermined one of said word lines and bit lines in said redundancy memory cell array.

3. A semiconductor memory device according to claim 2, wherein said control means is coupled to said poststage decoder means for comparing each of said input upper address bits with each of said programmed upper address bits, for outputting a control signal for inhibiting the decoding operation of said poststage decoder means and for placing said second selection means in an active state when each of said input upper address bits coincides with each of said programmed upper address bits.

4. A semiconductor memory device according to claim 1, wherein said first selection means comprises first decoder means, coupled to said regular memory cell array, for decoding said input upper address bits and said input lower address bits, and wherein said second selection means comprises second decoder means, coupled to said redundancy memory cell array, for decoding said input lower address bits.

5. A semiconductor memory device according to claim 4, wherein said control means is coupled to said first and second decoder means for comparing each of said input upper address bits and outputting the control signal, for inhibiting the decoding operation of said first decoder means and for placing said second decoder means in an active state when each of said input upper address bits coincides with each of said programmed upper address bits.