Method for zero byte time slot interchange
First Claim
1. In a data transmission system having first and second digital switching systems connected via T-carrier line facilities for the bidirectional transmission of data, each said switching system including a method for Zero Byte Time Slot Interchange (ZBTSI), said ZBTSI method comprising the steps of:
- first determining whether there is a single all zero octet contained in a plurality of frames of said data, said all zero octet being an octet containing 8-bits of zeros;
first storing an address representing said all zero octet in a predetermined location within said data and storing a contents of said predetermined location in said single all zero octet, said step of first storing being performed in response to a detection of said single all zero octet;
second determining whether there are multiple all zero octets in said plurality of frames of data, said step of second determining being performed in response to an absence of said detection of said one all zero octet;
third determining whether a certain intermediate storage octet is an all zero octet, said step of third determining being performed in response to a detection of multiple all zero octets;
second storing a contents of said intermediate storage octet into a first all zero octet, said step of second storing being performed in response to a lack of detection of said certain intermediate storage octets being all zero octets;
first chaining each of said all zero octets to said next all zero octet via insertion of an address representing a location of a next all zero octet into a contents said all zero octet, said step of first chaining being performed in response to said step of second storing;
first iterating said steps of second storing and first chaining for each of said plurality of frames of data;
fourth determining whether any of said intermediate storage octets are all zero octets, said fourth determining being performed in response to a detection of an intermediate storage octet being an all zero octet;
third storing a contents of an intermediate storage octet into a next previous intermediate storage octet, said step of third storing being performed in response to said step of fourth determining;
second chaining said each of said all zero octets to said a next all zero octet and said intermediate storage octet via insertion of an address representing a location of a next all zero octet into a contents of said all zero octet, said step of second chaining being performed in response to said step of third storing; and
second iterating said steps of third storing and second chaining.
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Abstract
This method is a scheme for suppressing excessive amounts of logic zeros transmitted via T-carrier line facilities between switching systems or channel banks. This scheme provides proper zero bit suppression for alternating mark inversion signalling (AMI). A proper AMI signal contains no more than 15 consecutive logic zero bit positions. This scheme provides for encoding and decoding a 4 frame octet group of an extended superframe. Logic ones are introduced into octets which would otherwise violate the AMI signalling rules. These logic ones are then removed by the receiving system and replaced with the indicated all zero octets before being given to down stream processing. Intermediate storage octets are utilized to contain addresses of an all zero octet. This scheme provides for minimal buffering at the encoding system, which facilitates error detection and correction by the decoding system.
13 Citations
30 Claims
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1. In a data transmission system having first and second digital switching systems connected via T-carrier line facilities for the bidirectional transmission of data, each said switching system including a method for Zero Byte Time Slot Interchange (ZBTSI), said ZBTSI method comprising the steps of:
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first determining whether there is a single all zero octet contained in a plurality of frames of said data, said all zero octet being an octet containing 8-bits of zeros; first storing an address representing said all zero octet in a predetermined location within said data and storing a contents of said predetermined location in said single all zero octet, said step of first storing being performed in response to a detection of said single all zero octet; second determining whether there are multiple all zero octets in said plurality of frames of data, said step of second determining being performed in response to an absence of said detection of said one all zero octet; third determining whether a certain intermediate storage octet is an all zero octet, said step of third determining being performed in response to a detection of multiple all zero octets; second storing a contents of said intermediate storage octet into a first all zero octet, said step of second storing being performed in response to a lack of detection of said certain intermediate storage octets being all zero octets; first chaining each of said all zero octets to said next all zero octet via insertion of an address representing a location of a next all zero octet into a contents said all zero octet, said step of first chaining being performed in response to said step of second storing; first iterating said steps of second storing and first chaining for each of said plurality of frames of data; fourth determining whether any of said intermediate storage octets are all zero octets, said fourth determining being performed in response to a detection of an intermediate storage octet being an all zero octet; third storing a contents of an intermediate storage octet into a next previous intermediate storage octet, said step of third storing being performed in response to said step of fourth determining; second chaining said each of said all zero octets to said a next all zero octet and said intermediate storage octet via insertion of an address representing a location of a next all zero octet into a contents of said all zero octet, said step of second chaining being performed in response to said step of third storing; and second iterating said steps of third storing and second chaining. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification