Still video frame store memory
First Claim
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1. A still video frame store memory, comprising:
- a plurality of memory banks, each of said banks comprising a plurality of data word storage locations, each of said locations being divisible into first and second byte locations;
analog-to-digital converter means for sampling a selected frame of a color video signal, and producing therefrom a set of luminance bytes characterized by a luminance digital rate and first and second sets of chrominance different bytes, each characterized by a chrominance digital rate less than said luminance digital rates; and
memory addressing means for;
a. storing said luminance bytes in said first byte locations of each of said banks;
b. storing said first chrominance difference bytes in alternate ones of said second byte locations in selected ones of said banks;
c. storing said second chrominance difference bytes in the remaining ones of said second byte locations in said selected banks, whereby the ratio of the number of byte locations storing said luminance bytes and storing said chrominance bytes corresponds to the ratio of said luminance and chrominance digital rates, wherein the byte locations in each bank are organizable in columns and rows of said byte locations, and wherein said addressing means is adaptable to perform indirect addressing, said addressing means further comprising;
a programmable offset register storing the bit length of the bytes in said banks;
a programmable address register including means for storing a column address byte, a row address byte and a plural bit code designating one of said plurality of said banks; and
a programmable control register including means for indicating whether said plural bit code is to be appended to said column address byte or to said row address byte and whether it is to be appended as the most significant bits or the least significant bits thereof;
means for receiving a column start address and a row start address and for receiving an indirect adjustment address, whereby said addressing means is adaptable to address a byte location corresponding to said starting row and column addresses during a first memory access cycle and to successively increment one or both of said row and column aaddresses in accordance with said indirect adjustment address once during each subsequent memory access cycle by an amount corresponding to the contents of said offset register.
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Abstract
A still video frame store memory includes four banks of random access memory storing two-byte words, the luminance data being stored in the high bytes of all banks and two chrominance difference signals being stored in the low bytes of two of the banks. The low bytes of the remaining two banks store compressed image data corresponding to the uncompressed image data stored in the other portion of the memory. Highly efficient indirect addressing is facilitated using an address word in which the two least significant bits specify a particular one of the four memory banks and another one of the least significant bits specifies either the high or low byte.
147 Citations
11 Claims
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1. A still video frame store memory, comprising:
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a plurality of memory banks, each of said banks comprising a plurality of data word storage locations, each of said locations being divisible into first and second byte locations; analog-to-digital converter means for sampling a selected frame of a color video signal, and producing therefrom a set of luminance bytes characterized by a luminance digital rate and first and second sets of chrominance different bytes, each characterized by a chrominance digital rate less than said luminance digital rates; and memory addressing means for; a. storing said luminance bytes in said first byte locations of each of said banks; b. storing said first chrominance difference bytes in alternate ones of said second byte locations in selected ones of said banks; c. storing said second chrominance difference bytes in the remaining ones of said second byte locations in said selected banks, whereby the ratio of the number of byte locations storing said luminance bytes and storing said chrominance bytes corresponds to the ratio of said luminance and chrominance digital rates, wherein the byte locations in each bank are organizable in columns and rows of said byte locations, and wherein said addressing means is adaptable to perform indirect addressing, said addressing means further comprising; a programmable offset register storing the bit length of the bytes in said banks; a programmable address register including means for storing a column address byte, a row address byte and a plural bit code designating one of said plurality of said banks; and a programmable control register including means for indicating whether said plural bit code is to be appended to said column address byte or to said row address byte and whether it is to be appended as the most significant bits or the least significant bits thereof; means for receiving a column start address and a row start address and for receiving an indirect adjustment address, whereby said addressing means is adaptable to address a byte location corresponding to said starting row and column addresses during a first memory access cycle and to successively increment one or both of said row and column aaddresses in accordance with said indirect adjustment address once during each subsequent memory access cycle by an amount corresponding to the contents of said offset register. - View Dependent Claims (2, 3, 4, 5, 11)
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6. A still video frame store memory comprising:
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a plurality of memory banks, each of said banks comprising a plurality of data word storage locations, each of said locations being divisible into first and second byte locations, a portion of some of said banks being reserved as a compressed image buffer; a host processor adaptable to receive compressed color video data, store it in said compressed image buffer, and to retrieve and expand it to produce therefrom luminance bytes characterized by a luminance digital rate and first and second chrominance difference bytes each characterized by a chrominance digital rate less than said luminance digital rate; and memory addressing means responsive to said host processor for; a. storing said luminance bytes in said first byte locations of each of said banks; b. storing said first chrominance difference bytes in alternate ones of said second byte locations in selected ones of said banks; c. storing said second chrominance difference bytes in the remaining ones of said second byte locations in said selected banks, wherein said compressed image buffer comprises the second byte locations of banks other than said selected banks, whereby the ratio of the number of byte locations storing said luminance bytes and storing said chrominance bytes corresponds to the ratio of said luminance and chrominance digital rates. - View Dependent Claims (7, 8, 9, 10)
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Specification