Fluid-cooled integrated circuit package

• US 4,758,926 A
• Filed: 03/31/1986
• Issued: 07/19/1988
• Est. Priority Date: 03/31/1986
• Status: Expired due to Fees

• Current Assignee: Microelectronics and Computer Technology Corporation
• Original Assignee: Microelectronics and Computer Technology Corporation
• Inventors: Gibson, David A., Herrell, Dennis J.
• Primary Examiner(s): Envall, Jr., Roy N.
• Assistant Examiner(s): Jennings, Derek S.
• Application Number:
  US06/846,087
• Time in Patent Office: 841 Days
• Field of Search: 361/385, 29/832, 29/840, 357/81, 357/82, 174/16 HS
• US Class Current: 361/699
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A package for enclosing, protecting and cooling semiconductor integrated circuit chips. The package includes a generally planar substrate with the chips positioned thereon. Signal connections are provided between at least some of the chips. A heat sink is positioned in contact with the chips and includes microchannels through which a cooling fluid flows for purposes of transferring heat generated by the chips to such fluid. Manifolds are provided to direct the fluid to and from the microchannels, and microcapillary slots may be formed on the heat sink surface adjacent the chips to receive liquid to generate attractive forces between the heat sink and chips to facilitate heat transfer. Circuitry is provided to distribute power through the package and to the chips.

Claims

1. A fluid-cooled integrated circuit package, comprising,

(a) a generally planar substrate forming a portion of the package and including

(i) a plurality of discrete integrated circuits thereon, and

(ii) signal interconnecting means for electrical communication between at least some of the integrated circuits,

(b) a heat sink generally in a parallel plane with the substrate (a), including

(i) microchannel means formed in the heat sink structure and adapted for fluid flow therethrough in juxtaposition with each of the integrated circuits (a)(i), and

(ii) manifold means for delivery of a cooling fluid to and from the microchannel means (b)(i),

(c) means for distributing power to the integrated circuits (a)(i), and

(d) means for enclosing the substrate (a), heat sink (b) and power distribution means (c) to form a unitary package, wherein the substrate (a) is a wafer of material selected from the group consisting of silicon, ceramic and metal, and the signal interconnecting means (a)(ii) comprises alternating layers of patterned electrically conductive metal and insulator on the inner surface of the substrate wafer.

2. The package of claim 1 wherein each of the integrated circuits (a)(i) has a plurality of electrical leads radiating from the integrated circuit.

3. The package of claim 2 wherein the electrical leads radiating from each integrated circuit (a)(i) are connected to the signal interconnecting means (a)(ii) of the substrate (a) and have a stepped cross-sectional profile so as to urge each integrated circuit into contact with the heat sink (b).

4. A fluid-cooled protective package for integrated circuits, comprising

(a) a generally planar substrate forming a portion of the package and including,

(i) a plurality of discrete integrated circuits arranged geometrically about the substrate, each such integrated circuit having a plurality of electrical leads radiating from the integrated circuit,

(ii) signal interconnecting means carried on the substrate for electrical communication between at least some of the integrated circuits in coaction with the electrical leads,

(b) a heat sink formed of a plurality of parallel layers of material selected from the group consisting of silicon, ceramic and metal and generally oriented in a parallel plane with the substrate (a), including

(i) a first layer having microchannels formed therein for fluid flow therethrough, the microchannels being in juxtaposition with the integrated circuits so as to conduct heat away from the integrated circuits,

(ii) at least a second layer having manifolds formed therein for delivery of a cooling fluid to and from each of the microchannels of the first layer, and

(iii) a third layer forming a cover for the manifolds of the second layer,

(c) means for distributing power to the integrated circuits, including,

(i) a plurality of metal stud members extending through the heat sink layers (b),

(ii) a plurality of metal buss strips connecting two or more of the metal stud members,

(iii) a plurality of capacitors, and

(iv) power redistribution decal means for electrically connecting with the metal stud members, the capacitors and the integrated circuits, and

(d) means for enclosing the substrate (a), the heat sink (b) and the power distributing means (c) to form a unitary package.

5. The protective package of claim 4 wherein the electrical leads radiating from each integrated circuit have a stepped cross-sectional profile so as to urge each integrated circuit into contact with the first layer of the heat sink (b).

6. The protective package of claim 4 wherein microcapillary slots are formed on the surface of the first heat sink layer (b)(i) between the microchannels and the integrated circuits to receive a liquid to achieve low thermal resistance between said layer and said integrated circuits.

7. The protective package of claim 4 wherein the substrate (a) is formed of a material selected from the group consisting of silicon, ceramic and metal.

8. The protective package of claim 4 wherein the metal stud members (c)(i) are oriented in parallel relation.

9. The protective package of claim 4 wherein at least some of the metal buss strips (c)(ii) extend sealably to the exterior of the package to form electrical power connectors.

10. The protective package of claim 4 wherein the signal interconnecting means (a)(ii) extends sealably through the package to form at least one exterior signal connector pad.

11. The protective package of claim 4 wherein means are carried on the package to connect an external source of cooling fluid to the manifolds (b)(ii).

12. The protective package of claim 4 wherein means are provided to solder together the substrate (a), heat sink layers (b)(i), (b)(ii) and (b)(iii), and enclosure means (d).

13. The protective package of claim 4 wherein the microchannels formed in the first heat sink layer (b)(i) are about 240 μ

m deep, about 80 μ

m wide, about 80 μ

m apart, and of a length corresponding to a lateral dimension of the integrated circuits.

14. The protective package of claim 6 wherein the microcapillary slots are from about 4 to about 10 μ

m deep, from about 3 to about 5 μ

m wide, and of a length corresponding to a lateral dimension of the integrated circuits.

15. A fluid-cooled integrated circuit package, comprising,

(a) a generally planar substrate forming a portion of the package and including

(i) a plurality of discrete integrated circuits thereon, and

(ii) signal interconnecting means for electrical communication between at least some of the integrated circuits,

(b) a heat sink generally in a parallel plane with the substrate (a), including

(i) microchannel means formed in the heat sink structure and adapted for fluid flow therethrough in juxtaposition with each of the integrated circuits (a)(i), and

(ii) manifold means for delivery of a cooling fluid to and from the microchannel means (b)(i),

(c) means for distributing power to the integrated circuits (a)(i), and

(d) means for enclosing the substrate (a), heat sink (b) and power distribution means (c) to form a unitary package, wherein the means (c) for distributing power to the integrated circuits (a)(i) comprises,

(i) a plurality of stud members in parallel alignment with one another and extending through the heat sink,

(ii) a plurality of metal buss strips interconnecting two or more of the stud members (i),

(iii) a plurality of capacitors,

(iv) power redistribution decal means for electrically connecting with the stud members (i), the capacitors (ii) and the integrated circuits.