Quasi content addressable memory
First Claim
1. A quasi content addressable memory circuit comprising:
- CAM means responsive to a first portion of a comparand, said CAM means being operative to develop a valid pointer signal and a pointer address when there is at least one favorable comparison between said first portion of said comparand and data stored within said CAM means;
comparator RAM means responsive to a second portion of said comparand, said valid pointer signal, and said pointer address, and operative to produce a match signal when enabled by said valid pointer signal and when the content of a memory location addressed by said pointer address compares favorably with said second portion of said comparand;
said comparator RAM means including bidirectional bus driver means responsive to a comparison signal and to a read/write signal for determining either a comparison or read/write mode of operation; and
said comparator RAM means including function select logic means responsive to a function control word for selecting one of a plurality of comparisons between the content of the memory location addressed by said pointer address and said second portion of said comparand to develop said match signal.
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Accused Products
Abstract
A quasi content addressable memory circuit including a CAM section, a RAM section, and a comparator. A first part of an incoming comparand is applied to the CAM section, while a second part of the incoming comparand is applied to the comparator. If there is a favorable comparison within the CAM section with the first part of the comparand, the CAM section develops a pointer which addresses the RAM. The output of the RAM is then compared to the second part of the comparand and, if a favorable comparison is made, a match flag is developed. Also disclosed are circuits for handling multiple responses by the CAM section, and a practical comparator RAM which combines the functions of the comparator and the RAM of the quasi content addressable memory circuit.
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Citations
6 Claims
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1. A quasi content addressable memory circuit comprising:
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CAM means responsive to a first portion of a comparand, said CAM means being operative to develop a valid pointer signal and a pointer address when there is at least one favorable comparison between said first portion of said comparand and data stored within said CAM means; comparator RAM means responsive to a second portion of said comparand, said valid pointer signal, and said pointer address, and operative to produce a match signal when enabled by said valid pointer signal and when the content of a memory location addressed by said pointer address compares favorably with said second portion of said comparand; said comparator RAM means including bidirectional bus driver means responsive to a comparison signal and to a read/write signal for determining either a comparison or read/write mode of operation; and said comparator RAM means including function select logic means responsive to a function control word for selecting one of a plurality of comparisons between the content of the memory location addressed by said pointer address and said second portion of said comparand to develop said match signal. - View Dependent Claims (2, 3)
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4. A quasi content addressable memory circuit comprising:
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CAM means including a plurality of content addressable memory locations, each CAM memory location being formed of a CAM memory location content field and an associated location pointer; said CAM means being responsive to a CAM comparand portion of a comparand for comparing said CAM comparand portion in parallel to all of the memory location content fields and for generating a pointer valid signal and a RAM pointer address developed from the corresponding associated location pointer at a particular CAM memory location content field when said CAM comparand portion compares favorably with the contents of at least one of said CAM memory location content fields; RAM means including a plurality of randomly addressable RAM memory locations, each RAM memory location being formed of a RAM content field, said RAM means being responsive to said RAM pointer address for generating a RAM data output corresponding to a particular RAM content field addressed by said RAM pointer address; and comparison means for comparing a RAM comparand portion of said comparand with said RAM data output and for generating a match flag when said RAM comparand portion compares favorable with said RAM data output, said comparison means being responsive to said pointer valid signal for enabling and disabling of the same. - View Dependent Claims (5, 6)
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Specification