Quasi content addressable memory

• US 4,758,982 A
• Filed: 01/08/1986
• Issued: 07/19/1988
• Est. Priority Date: 01/08/1986
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Price, Simon M.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/817,230
• Time in Patent Office: 923 Days
• Field of Search: 365/49, 364/200 MS File, 364/900 MS File
• US Class Current: 711/108
• CPC Class Codes: G06F 16/90339 by using parallel associative memories or content-addressable memories
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A quasi content addressable memory circuit including a CAM section, a RAM section, and a comparator. A first part of an incoming comparand is applied to the CAM section, while a second part of the incoming comparand is applied to the comparator. If there is a favorable comparison within the CAM section with the first part of the comparand, the CAM section develops a pointer which addresses the RAM. The output of the RAM is then compared to the second part of the comparand and, if a favorable comparison is made, a match flag is developed. Also disclosed are circuits for handling multiple responses by the CAM section, and a practical comparator RAM which combines the functions of the comparator and the RAM of the quasi content addressable memory circuit.

Claims

1. A quasi content addressable memory circuit comprising:

CAM means responsive to a first portion of a comparand, said CAM means being operative to develop a valid pointer signal and a pointer address when there is at least one favorable comparison between said first portion of said comparand and data stored within said CAM means;

comparator RAM means responsive to a second portion of said comparand, said valid pointer signal, and said pointer address, and operative to produce a match signal when enabled by said valid pointer signal and when the content of a memory location addressed by said pointer address compares favorably with said second portion of said comparand;

said comparator RAM means including bidirectional bus driver means responsive to a comparison signal and to a read/write signal for determining either a comparison or read/write mode of operation; and

said comparator RAM means including function select logic means responsive to a function control word for selecting one of a plurality of comparisons between the content of the memory location addressed by said pointer address and said second portion of said comparand to develop said match signal.

2. A quasi content addressable memory circuit as recited in claim 1 wherein said comparator RAM means is a first comparator RAM means producing a first match signal, and further comprising a second comparator RAM means responsive to a third portion of said comparand, said pointer address, and said first match signal of said first comparator RAM means, said second comparator RAM means being operative to produce a second match signal when enabled by said first match signal and when the content of a memory location addressed by said pointer address compares favorably with said third portion of said comparand.

3. A quasi content addressable memory circuit as recited in claim 1 wherein said comparator RAM means includes a plurality of comparator RAM circuits, where a first comparator RAM circuit is responsive to a part of said second portion of said comparand, said valid pointer signal, and said pointer address and is operative to produce a match signal when enabled by said valid pointer signal and when the contents of a memory location addressed by said pointer address compares favorably with said part of said second portion of said comparand;

and where the remainder of said comparator RAM circuits are responsive to parts of said second portion of said comparand, a match signal from another comparator RAM circuit, and said pointer address, and are operative to produce their own match signal when the content of one of their memory locations addressed by said pointer address compares favorably with the part of said second portion of said comparand to which they are responsive.

4. A quasi content addressable memory circuit comprising:

CAM means including a plurality of content addressable memory locations, each CAM memory location being formed of a CAM memory location content field and an associated location pointer;

said CAM means being responsive to a CAM comparand portion of a comparand for comparing said CAM comparand portion in parallel to all of the memory location content fields and for generating a pointer valid signal and a RAM pointer address developed from the corresponding associated location pointer at a particular CAM memory location content field when said CAM comparand portion compares favorably with the contents of at least one of said CAM memory location content fields;

RAM means including a plurality of randomly addressable RAM memory locations, each RAM memory location being formed of a RAM content field, said RAM means being responsive to said RAM pointer address for generating a RAM data output corresponding to a particular RAM content field addressed by said RAM pointer address; and

comparison means for comparing a RAM comparand portion of said comparand with said RAM data output and for generating a match flag when said RAM comparand portion compares favorable with said RAM data output, said comparison means being responsive to said pointer valid signal for enabling and disabling of the same.

5. A quadi content addressable memory circuit as recited in claim 4 wherein said CAM means further includes multiple response handling means responsive to the comparisons between said CAM comparand portion and said CAM memory locations, and operative to produce a series of RAM pointer addresses when there are multiple favorable comparisons.

6. A quasi content addressable memory circuit as recited in claim 5 wherein said multiple response handling means includes a priority encoder which prioritizes and sequences a series of RAM pointer addresses when there are multiple favorable responses.