Microprocessor oriented configurable logic element
First Claim
1. A configurable logic element comprising:
- means for receiving a first plurality of N binary input signals;
means for receiving a second plurality of M binary feedback signals;
means for selecting K of said M+N binary signals (where K≦
M+N);
configurable combinational logic means for receiving said K binary signals from said means for selecting, said configurable combinational logic means having a plurality of configurations for generating selected binary output signals;
a first configurable storage circuit for receiving selected ones of said binary output signals of said configurable combinational logic means and selected ones of said N binary input signals and for generating said M binary feedback signals, said configurable storage circuit having a plurality of configurations;
a configurable select logic comprising means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit and means for selecting output signals from among the signals received by said select logic; and
means for reading the status of a selected one of said output signals of said combinational logic means and said M feedback signals.
1 Assignment
0 Petitions
Accused Products
Abstract
A microprocessor controlled configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, a configurable status buffer, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip-flop with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output from among the output signals of the combinational logic element and the storage circuit. The configurable status buffer may be configured to provide status information on selected important internal signals of the configurable logic circuit. A microprocessor interface structure may access an array of these configurable logic circuits through the status buffer to read different internal output signals from different circuits in the array. Providing separate input and output to a microprocessor leaves the storage element free for other uses and does not require the logic provided by the logic elements.
-
Citations
11 Claims
-
1. A configurable logic element comprising:
-
means for receiving a first plurality of N binary input signals; means for receiving a second plurality of M binary feedback signals; means for selecting K of said M+N binary signals (where K≦
M+N);configurable combinational logic means for receiving said K binary signals from said means for selecting, said configurable combinational logic means having a plurality of configurations for generating selected binary output signals; a first configurable storage circuit for receiving selected ones of said binary output signals of said configurable combinational logic means and selected ones of said N binary input signals and for generating said M binary feedback signals, said configurable storage circuit having a plurality of configurations; a configurable select logic comprising means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit and means for selecting output signals from among the signals received by said select logic; and means for reading the status of a selected one of said output signals of said combinational logic means and said M feedback signals. - View Dependent Claims (2, 3, 4, 9, 10, 11)
-
-
5. A configurable logic element comprising:
-
means for receiving a first plurality of N binary input signals; means for receiving a second plurality of M binary feedback signals; means for selecting K of said M+N binary signals (where K≦
M+N);configurable combinational logic means for receiving said K binary signals from said means for selecting, said configurable combinational logic means having a plurality of configurations for generating selected binary output signals; a first configurable storage circuit for receiving selected ones of said binary output signals of said configurable combinational logic means and selected ones of said N binary input signals and for generating said M binary feedback signals, said configurable storage circuit having a plurality of configurations; a configurable select logic comprising means for receiving said output signals generated by said combinational logic means and said M binary signals generated by said configurable storage circuit and means for selecting output signals from among the signals received by said select logic; a second storage circuit for storing a storage data signal and for providing an output signal representing said storage data signal; and configurable means for providing said output signal of said second storage circuit to said means for receiving a first plurality of N binary input signals. - View Dependent Claims (6, 7, 8)
-
Specification