Integrated circuit in complementary circuit technology
First Claim
1. A method for the manufacture of an integrated circuit comprising the steps of forming on a body (1) of doped semiconductor material of a first conductivity type which is covered on a boundary surface (1a) by field insulation regions (3a through 3e) and gate insulation regions (S1 through S4) a tub-shaped zone (2) of a second conductivity type which extends up to the boundary surface (1a), applying a polycrystalline silicon layer to the insulation layer formed by photolithographic processes so that gates (6, 16) of field effect transistors are formed on at least one gate insulation region (S1) above the tub-shaped zone (2) and on a further gate insulation region (S4) outside of said zone (2), forming source and drain regions (14, 15) of the field effect transistors which lie outside of the zone (2) and the connecting region (23) of the zone (2) by an ion implantation (Im1) with the part of the insulation layer lying above the tub-shaped zone (2) except for a sub-region above a connecting region (23) of this zone covered by an implantation mask (L1) such as a photoresist layer, forming the source and drain regions (4, 5) of the field effect transistors lying within the zone by a further ion implantation (Im2) wherein the part of the insulation layer lying outside the tub-shaped zone (2) is covered by a further implantation mask (L2) of a further photoresist layer, and one of the gate insulation regions (S2) which is mounted above the tub-shaped zone is covered by the implantation masks of both ion implantations, and applying an intermediate insulation layer (8) and forming it with windows extending to the boundary layer (1a) of the body (1), above the source and drain regions of the field effect transistors, above the connecting region (23) of the zone and above the gate insulation region (S2) which are covered by both implantation masks, and applying conductive coatings (9, 12, 24, 18 and 20) to the intermediate insulation layer (8) which respectively contact the parts of the body (1) in the regions of the windows which lie therebelow, and applying terminals to these conductive coatings so as to apply supply voltage and the reference voltage.
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Abstract
An integrated circuit in complementary circuit technology comprising two field effect transistors (T1, T2) of different channel types with the first one (T2) mounted in a doped semiconductor body (1) having a first conductivity type and the other FET (T1) mounted in a semiconductor zone 2 of a second conductivity type which is arranged in said body. The object is to provide a protection against thermal overloads which can appear due to "latch up" influences when overvoltages at the one connecting region of the field effect transistor (T1) mounted in the semiconductor zone occur. This is accomplished by the mounting of a metal contact (12) on the surface of a semiconductor region (2'"'"') inserted into the semiconductor body 1 and doped oppositely thereto with such metal contact forming a Schottky diode (D) with the semiconductor region (2'"'"') which can be connected to the connecting region of the field effect transistor T1 mounted in the semiconductor region 2 whereas the semiconductor region (2'"'"') is electrically connected to the supply voltage (VDD). The circuits are applied in CMOS circuits.
18 Citations
1 Claim
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1. A method for the manufacture of an integrated circuit comprising the steps of forming on a body (1) of doped semiconductor material of a first conductivity type which is covered on a boundary surface (1a) by field insulation regions (3a through 3e) and gate insulation regions (S1 through S4) a tub-shaped zone (2) of a second conductivity type which extends up to the boundary surface (1a), applying a polycrystalline silicon layer to the insulation layer formed by photolithographic processes so that gates (6, 16) of field effect transistors are formed on at least one gate insulation region (S1) above the tub-shaped zone (2) and on a further gate insulation region (S4) outside of said zone (2), forming source and drain regions (14, 15) of the field effect transistors which lie outside of the zone (2) and the connecting region (23) of the zone (2) by an ion implantation (Im1) with the part of the insulation layer lying above the tub-shaped zone (2) except for a sub-region above a connecting region (23) of this zone covered by an implantation mask (L1) such as a photoresist layer, forming the source and drain regions (4, 5) of the field effect transistors lying within the zone by a further ion implantation (Im2) wherein the part of the insulation layer lying outside the tub-shaped zone (2) is covered by a further implantation mask (L2) of a further photoresist layer, and one of the gate insulation regions (S2) which is mounted above the tub-shaped zone is covered by the implantation masks of both ion implantations, and applying an intermediate insulation layer (8) and forming it with windows extending to the boundary layer (1a) of the body (1), above the source and drain regions of the field effect transistors, above the connecting region (23) of the zone and above the gate insulation region (S2) which are covered by both implantation masks, and applying conductive coatings (9, 12, 24, 18 and 20) to the intermediate insulation layer (8) which respectively contact the parts of the body (1) in the regions of the windows which lie therebelow, and applying terminals to these conductive coatings so as to apply supply voltage and the reference voltage.
Specification
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- Resources
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Current AssigneeSiemens AG
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Original AssigneeSiemens AG
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InventorsSchuetz, Alfred, Pfleiderer, Hans-Joerg
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Primary Examiner(s)NOT, DEFINED
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Application NumberUS06/942,023Time in Patent Office592 DaysField of Search357/42, 357/15, 357/15 M, 357/15 R, 29/571, 29/576 B, 29/576 W, 29/577 C, 437/57, 437/41US Class Current438/200CPC Class CodesH01L 21/28518 the conductive layers compr...H01L 27/0727 in combination with diodes,...H01L 27/0925 comprising an N-well only i...
