High-speed, bootstrap driver circuit

• US 4,760,282 A
• Filed: 11/13/1986
• Issued: 07/26/1988
• Est. Priority Date: 11/13/1986
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Carey, Brian R., Kuo, James R.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/930,594
• Time in Patent Office: 621 Days
• Field of Search: 307/270, 307/263, 307/878, 307/254, 307/482, 307/296 R, 307/296.1, 330/156
• US Class Current: 326/90
• CPC Class Codes: H03K 19/00307 in bipolar transistor circuits
• CPC Class Codes: H03K 19/0133 by bootstrapping, i.e. by positive feed-back
• CPC Class Codes: H03K 19/0826 one of the states being the high impedance or floating state
• CPC Class Codes: H03K 5/02 by amplifying H03K5/04 takes precedence

Abstract

A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.

Claims

1. A circuit for driving digital signals from a signal source through an output terminal onto a line, said circuit comprising:

an output transistor having an emitter terminal connected to said output terminal, a base terminal connected to a first current source, and a collector terminal coupled to a first voltage supply source;

a second transistor having an emitter terminal connected to said base terminal of said output transistor, a base terminal connected to a second current source, and a collector terminal coupled to said first voltage supply source;

switching means connected to said output terminal, said base terminal of said output transistor and said base terminal of said second transistor, said switching mean coupling and uncoupling said output terminal, and said base terminals of said output and second transistors to ground, responsive to a data signal from said signal source; and

capacitive means connected to said base terminal of said output transistor and to said base terminal of said second transistor through a first impedance means, said capacitive means raising the voltage to said base terminal of said second transistor to decrease the switch-on times of said output and second transistors.

2. The driving circuit as in claim 1 further comprising a second impedance means, said second impedance means and said second current source.

3. The driving circuit as in claim 1 further comprising a third transistor, said third transistor having an emitter terminal connected to a node between said first and second impedance means, a base terminal connected to said second current source, and a collector terminal connected to a collector terminal of said second transistor.

4. The driving circuit as in claim 3 wherein the impedance of said first impedance means is much smaller than the impedance of said second impedance means.

5. The driving circuit as in claim 3 wherein said switching means comprises a fourth transistor having an emitter terminal coupled to ground, a collector terminal connected to said base terminal of said second transistor through a first rectifying means, and a base terminal connected to said signal source.

6. The driving circuit as in claim 5 wherein said switching means further comprises a fifth transistor having an emitter terminal coupled to ground, a collector terminal connected to said base terminal of said second transistor through a second rectifying means and third impedance means, and a base terminal connected to said signal source.

7. The driving circuit as in claim 6 wherein said switching means further comprises a sixth transistor having an emitter terminal coupled to ground, a collector terminal connected to said output terminal through a third

rectifying means, and a base terminal connected to said emitter terminal of said fourth transistor.

8. The driving circuit as in claim 1 wherein said output and second transistors are PNP transistors, each having its base and collector regions connected by a Schottky diode.

9. A digital logic circuit comprising:

a first transistor having an emitter terminal connected to an output terminal, a base terminal connected to a first current source, and a collector terminal coupled to a first voltage supply source;

a second transistor having an emitter terminal connected to said base terminal of said first switching transistor, a base terminal connected to a second current source, and a collector terminal coupled to said first voltage supply source;

switching means connected to said output terminal, said base terminal of said first transistor and said base terminal of said second transistor, said switching means coupling and uncoupling said emitter and base terminals of said first transistor and said base terminal of said second transistor to a second voltage supply reference responsive to a digital logic signal from a signal source; and

capacitive means connected to said base terminal of said output transistor and to said base terminal of said second transistor through a first impedance means, said capacitive means raising the voltage to said base terminals of said first and second transistors as said first transistor turns on to decrease the switch-on times of said first and second transistors.

10. The circuit as in claim 9 further comprising a second impedance means, said second impedance means connected between said first impedance means and said second current source.

11. The circuit as in claim 10 further comprising a third transistor, said third transistor having an emitter terminal connected to a node between said first and second impedance means, a base terminal connected to said second current source, and a collector terminal connected to said collector terminal of said second transistor.

12. The circuit as in claim 11 wherein the impedance of said first impedance means is much smaller than the impedance of said second impedance means.

13. The circuit as in claim 12 wherein said switching means comprises a fourth transistor having an emitter terminal coupled to ground, a collector terminal connected to said base terminal of said second transistor through a first rectifying means, and a base terminal connected to said signal source.

14. The circuit as in claim 13 wherein said switching means further comprises a fifth transistor having an emitter terminal coupled to said second voltage supply source, a collector terminal connected to said base terminal of said second transistor through a second rectifying means and third impedance means, and a base terminal connected to said signal source.

15. The circuit as in claim 14 wherein said switching means further comprises a sixth transistor having an emitter terminal coupled to said second voltage supply source, a collector terminal connected to said emitter terminal of said first transistor through a third rectifying means, and a base terminal connected to said emitter terminal of said fourth transistor.

16. The circuit as in claim 10 wherein said first, second and third transistors are PNP transistors, each having its base and collector regions connected by a Schottky diode.