Programmable tester with bubble memory

• US 4,760,329 A
• Filed: 04/23/1987
• Issued: 07/26/1988
• Est. Priority Date: 04/23/1987
• Status: Expired due to Term

• Current Assignee: Grumman Aerospace Corporation (Northrop Grumman Corporation)
• Original Assignee: Grumman Aerospace Corporation (Northrop Grumman Corporation)
• Inventors: Andreano, Richard J.
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US07/041,572
• Time in Patent Office: 460 Days
• Field of Search: 324/73 R, 324/73 AT, 324/73 PC, 324/158 F, 371/15, 371/16, 371/20, 371/25, 364/580
• US Class Current: 714/32
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns

Abstract

A portable programmable electronic tester capable of automatically testing a large number of different types of electronic units is disclosed. The operation of the tester is governed by a self-contained microcomputer. A programmable stimulus subsystem provides desired stimuli to a unit under test and a programmable response measuring subsystem measures specified output parameters of the unit under test. A programmable switching subsystem selectively connects the unit under test to the stimulus and response measuring subsystems via an interface device adapted to connect the unit under test to the tester. A test program designed to test the operating characteristics of a particular unit under test is stored in a bubble memory cassette.

Claims

1. Programmable test apparatus comprising:

(a) connecting means for receiving interface means configured to adapt a unit under test to said test apparatus, said interface means cooperating with bubble memory means, the latter storing a plurality of test programs written in a high level language and converted to interpretive code format for selectively testing the operation of said unit under test;

(b) system bus means;

(c) microcomputer means operatively connected to said system bus means and including means for executing each test program;

(d) memory means associated with said microcomputer means operatively connected to said system bus means and including means for storing an interpreter program for interpreting the interpretive code format test program;

(e) programmable stimulus generating means operatively connected via said system bus means to said microcomputer means;

(f) programmable response measuring means operatively connected via said system bus means to said microcomputer means;

(g) switching means included in the stimulus generating and response measuring for selectively connecting said stimulus generating means and said response measuring means via said interface means to said unit under test, said switching means responsive to and operatively connected via a switching control bus means to said microprocessor control means;

(h) programmable digital signal generating means operatively connected via said system bus means to said microcomputer means and including means for effecting data communication directly via said interface means with said unit under test; and

(i) terminal means operatively connected to said microcomputer means for initiating execution of said test program and displaying the results thereof.

2. Programmable test apparatus as recited in claim 1 wherein the high level language in ATLAS.

3. Programmable test apparatus comprising:

(a) connecting means for receiving interface means configured to adapt a unit under test to said test apparatus, said interface means cooperating with bubble memory means for storing a plurality of test programs written in a high level language and converted to interpretive code format for selectively testing the operation of said unit under test;

(b) system bus means;

(c) microcomputer means operatively connected to said system bus means and including means for executing each test program;

(d) memory means associated with said microcomputer means operatively connected to said system bus means and including means for storing an interpreter program for interpreting the interpretive code format test program;

(e) programmable stimulus generating means operatively connected via said system bus means to said microcomputer means;

(f) programmable response measuring means operatively connected via said system bus means to said microcomputer means;

(g) first switching means integrally distributed amongst the stimulus generating means and the response measuring means for selectively connecting preselected stimulating generating means and response measuring means to an interconnecting analog switching bus, under direction of said microcomputer means; and

(h) second switching means connected between the analog switching bus and the unit under test for routing signals to preselected I/O lines of the unit under test.

4. The structure set forth in claim 3 wherein the high level language is ATLAS.

5. The structure set forth in claim 3 together with terminal means operatively connected to said microcomputer means for initiating execution of said test program and displaying the results thereof.