Display controller

• US 4,760,387 A
• Filed: 01/31/1986
• Issued: 07/26/1988
• Est. Priority Date: 03/19/1985
• Status: Expired due to Term

• Current Assignee: Ascii Corp. (Kadokawa Dwango Corp.), Nippon Yusen Kabushiki Kaisha
• Original Assignee: Ascii Corp. (Kadokawa Dwango Corp.), Nippon Yusen Kabushiki Kaisha
• Inventors: Kaneko, Makoto, Ishii, Takatoshi
• Primary Examiner(s): Brigance, Gerald L.
• Assistant Examiner(s): FATAHI YAR, MAHMOUD
• Application Number:
  US06/824,953
• Time in Patent Office: 907 Days
• Field of Search: 340/703, 340/716, 340/718, 340/717, 340/720, 340/784, 340/811, 340/814, 364/900
• US Class Current: 345/3.1
• CPC Class Codes: G06F 3/1475 with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory
• CPC Class Codes: G09G 2360/04 Display device controller operating with a plurality of display units
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3644 with the matrix divided into sections
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes
• CPC Class Codes: G09G 5/222 Control of the character-code memory

Abstract

A display controller displays an image on either of a CRT display unit and a liquid crystal display unit (LCD) having upper and lower screens in accordance with image data stored in a memory. When a CRT display unit is driven, an address generating circuit calculates at the beginning of each horizontal scanning an address of the memory corresponding to the leftmost display position on the current horizontal scanning line in accordance with the vertical position of the horizontal scanning line and the number of display positions on a horizontal scanning line, and stores data representing the address in a first register. The data in the first register is incremented in accordance with the horizontal scanning and fed to the memory to read the image data. When the LCD is driven, the address generating circuit calculates at the beginning of each horizontal scanning two addresses of the memory corresponding respectively to the left most display positions on the current horizontal scanning lines on the upper and lower screens. In this case, the first one is obtained in accordance with the vertical position of the current horizontal scanning line on the upper screen and the number of display positions on a horizontal scanning line, while the second one is obtained by adding the number of display positions on the upper screen to the calculated first address.

Claims

1. A display controller capable of selectively driving a selected one of a first and a second display unit, the first display unit having a display screen comprised of a scanning-type screen which provides M rows of N columns of display positions thereon, the second display unit having a display screen constituted by upper and lower scanning-type screens, each of which provides P rows of Q columns of display positions thereon, the display controller being further connected to memory means having a plurality of addresses, each for storing display data relating to an image to be displayed at a respective one of the display positions of the selected display unit, said display controller comprising:

(a) display unit designating means for designating one of said first and second display units, said designation means producing a first designation signal when the first display unit is selected, and producing a second designation signal when the second display unit is selected;

(b) tiiming signal generating means, responsive to said first designation signal, for generating first synchronization signals is response to said first designation signal to be supplied to the first display unit for scanning the screen thereof, said timing signal generating means being further responsive to said second designation signal to generate second synchronization signals in response to said second designation signal, to be supplied to the second display unit for scanning the upper and lower screens thereof;

(c) address data generating means, responsive to said first designation signal, for generating a first series of address data representative of addresses of the memory means and sequentially outputting said generated address data to the memory means in accordance with the scanning of the display screen of the first display unit, said address data generating means being further responsive to said second designation signal for generating a second series of address data representative of those of the addresses of the memory means corresponding to the upper screen and a third series of address data representative of those of the addresses of the memory means corresponding to the lower screen, said address data generating means alternately outputting, responsive to said second designation signal, each of said second series of address data and each of said third series of address data to the memory means in accordance with scanning of the upper and lower screens; and

(d) display signal generating means, responsive to said first designation signal for generating a first display signal to be supplied to the first display unit based on data read from the memory means in accordance with said first series of address data, said display signal generating means being further responsive to said second designation signal to generate second and third display signals to be supplied to the second display unit based on data read from the memory means in accordance with said second and third series of address data, said second and third display signals being used to display images on the upper and lower screens of said second display unit, respectively.

2. A display controller according to claim 1, wherein the first display unit is a CRT display unit and the second display unit is a liquid crystal display unit.

3. A display controller according to claim 2, wherein said address data generating means includes means for generating said third series of address data as an address data disposed (P x Q) addresses apart from respective ones of the addresses of the memory means indicated by said second series of address data, where P and Q are the number of rows and columns of the memory means, respectively.

4. A display controller according to claim 3 further comprising counter means, operable in synchronism with said synchronization signals generated by said timing signal generating means, for producing a data "V" representative of the row of the display position currently scanned on the display screen of the designated display unit, and wherein said address data generating means comprises:

calculation means, responsive to said first designation signal, for calculating a value of "N×

V", said calculation means being further responsive to said second designation signal to calculate a value of "Q×

V" and of "Q×

V+P×

Q";

first address register means, responsive to said first designation signal, for receiving a value of said "N×

V" before beginning each horizontal scan of the display screen of the first display unit, said first address register means being further responsive to said second designation means for receiving a value of said "Q×

V" as an initial address before beginning each horizontal scan of the display screen of the second display unit;

second address register means responsive to said second designation signal for receiving a value of said "Q×

V+P×

Q" as an initial address before beginning each horizontal scan of the display screen of the second display unit;

mean responsive to said first designation signal for incrementing the contents of said first address register means in accordance with the horizontal scanning of the display screen of the first display unit and outputting the contents of said first address register means as said first series of address data; and

means responsive to said second designation signal for incrementing the contents of both of said first and second address register means in accordance with the horizontal scanning of the upper and lower screens of the second display unit and alternately outputting the contents of said first and second address register means as said second and third series of address data, respectively.

5. A display controller according to claim 4, wherein each of the display data stored in the memory means comprises a character code representative of a character to be displayed in the corresponding display position and a pair of color codes for respectively designating foreground and background colors of said character, and wherein said display signal generating means comprises:

character generator means responsive to each of the character codes read from the memory means for generating a bit pattern of a character represented by the corresponding character code;

selector means for selectively outputting color codes read from the memory means with said character code in accordance with said bit pattern; and

first conversion means for converting each of the color codes outputted from said selector means into corresponding color component signals to be outputted as said first display signal.

6. A display controller according to claim 5, wherein said display signal generating means further comprises second conversion means responsive to said second designation signal for converting said color component signals outputted from said first conversion means into a corresponding luminance signal, and a signal distribution means for outputting those of the luminance signals corresponding to the display positions on the upper screen as said second display signal and outputting those of the luminance signals corresponding to the display positions on the lower screen as said third display signal.