Peripheral interrupt interface for multiple access to an interrupt level

• US 4,760,516 A
• Filed: 11/25/1986
• Issued: 07/26/1988
• Est. Priority Date: 11/25/1986
• Status: Expired due to Term

• Current Assignee: Eicon Networks Corporation (Enghouse Systems Limited)
• Original Assignee: Dialogic, Inc. (Enghouse Systems Limited)
• Inventors: Zwick, Nicholas
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/934,714
• Time in Patent Office: 609 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/260
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence

Abstract

Circuitry which permits a plurality of peripherals to share a single interrupt signal line in computer systems and thereby increase the number of peripherals which can be supported.

Claims

1. Apparatus connected between a peripheral and an interrupt signal line in a computer system, said apparatus comprising:

first means having an output connected to said interrupt signal line and being responsive to a first control signal from said peripheral for providing a transition from a first to a second voltage at said interrupt signal line, said first means once enabled also maintaining said second voltage at said interrupt signal line, said first means being further responsive to a second control signal from said computer system for disabling said first means; and

second means having an output connected to said interrupt signal line and being responsive to said second control signal for driving said interrupt signal line back to said first voltage.

2. Apparatus connected between a peripheral and an interrupt signal line in a computer system, said apparatus comprising:

a flip flop having first and second input terminals and an output terminal, said first input terminal being responsive to a first control signal from the peripheral and said second input terminal being responsive to a second control signal from said computer system;

a first transistor connected to said flip-flop output terminal, said first transistor having emitter and collector terminals, said emitter terminal being connected to said interrupt signal line;

a first resistor connected between said first transistor collector terminal and a first reference potential;

a second resistor connected between said interrupt signal line and a second reference potential, whereby said interrupt signal line is driven from said second reference potential to a voltage in response to said first control signal; and

second means having an output connected to said interrupt signal line and being responsive to said second control signal for driving said interrupt signal line back to said second reference potential.

3. The apparatus of claim 2 wherein said flip-flop is of the set-reset type.

4. The apparatus of claim 2 wherein said first control signal produces a first logic level at said flip-flop output terminal which turns said first transistor on thereby establishing a current flow from said first reference potential through said first and second resistors to said second reference potential.

5. The apparatus of claim 2 wherein the second means comprises a second transistor responsive to the second control signal, the second transistor having collector and emitter terminals respectively connected to said interrupt signal line and said second reference potential.

6. The apparatus of claim 5 wherein said second control signal produces a second logic level at said flip-flop output which turns said first transistor off and turns said second transistor on thereby shunting said signal interrupt line to said second reference potential.

7. Apparatus connected between a multiplicity of peripherals and an interrupt signal line in a computer system, said apparatus comprising:

at least one interface apparatus connected between one of said multiplicity of peripherals and said interrupt signal line which comprises;

a flip-flop having first and second input terminals and an output terminal, said first input terminal being responsive to a first control signal from said one of said multiplicity of peripherals and said second input terminal being responsive to a second control signal from said computer system;

a first transistor connected to said flip flop output terminal, said first transistor having emitter and collector terminals, said emitter terminal being connected to said interrupt signal line;

a first resistor connected between said first transistor collector terminal and a first reference potential;

a second resistor connected between said interrupt signal line and a second reference potential, whereby said interrupt signal line is driven from said second reference potential to a voltage in response to said first control signal; and

second means having an output connected to said interrupt signal line and being responsive to said second control signal for driving said interrupt signal line back to said second reference potential; and

at least one further interface apparatus connected between another one of said multiplicity of peripherals and said interrupt signal line which comprises;

a flip flop having first and second input terminals and an output terminal, said first input terminal being responsive to a first control signal from said another one of said multiplicity of peripherals and said second input terminal being responsive to another second control signal from said computer system;

a first transistor connected to said flip flop output terminal, said first transistor having emitter and collector terminals, said emitter terminal being connected to said interrupt signal line;

a first resistor connected between said first transistor collector terminal and a first reference potential;

said emitter terminal also being connected to said second reference potential, whereby said interrupt signal line is driven from said second reference potential substantially to said voltage in response to said first control signal; and

second means having an output connected to said interrupt signal line and being responsive to said another second control signal for driving said interrupt signal line back to said second reference potential.