Bi-directional databus system for supporting superposition of vector and scalar operations in a computer

• US 4,760,518 A
• Filed: 02/28/1986
• Issued: 07/26/1988
• Est. Priority Date: 02/28/1986
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Scientific Computer Systems Corporation
• Inventors: Thompson, William B., Cook, Erick M., Haakmeester, Mark A., Schuh, Jennifer S., Phelps, Andrew E., Potash, Hanan
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Harrell, Robert B.
• Application Number:
  US06/835,129
• Time in Patent Office: 879 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/300, 364/730
• US Class Current: 710/107
• CPC Class Codes: G06F 15/8084 Special arrangements thereof, e.g. mask or switch
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A bi-directional databusing system is used in a computer that superposes vector and scalar operations. The computer consists of a main memory, a plurality of pipelined functional units, and a buffer for staging scalar and vector data objects between the main memory and the functional units. The busing system supports two-way data transfer during each of a succession of bus transfer cycles in which data is transferred to the buffer during one phase of a cycle, and from the buffer during a second cycle phase. The busing system includes three sets of bi-directional memory databuses, one for transferring scalar data objects between the main memory and buffer unit, and the other two for transferring vector data objects between the main memory and the buffer. The bus system also includes a set of bi-directional function buses, each for transferring scalar and vector data objects between the buffer and the functional units, with the ratio of the number of data objects transferred to the functional units during a transfer cycle to the number of data objects transferred to the buffer during the same cycle corresponding to a predetermined parametric value.

Claims

1. In a computer including a memory for storing vector data objects and scalar data objects, said vector data objects each including an ordered array of vector data elements, functional units for performing arithmetic and logical operations on vector and scalar data objects, and a buffer including vector registers for temporary storage of vector data objects and scalar registers for temporary storage of scalar data objects, wherein the improvement is a bi-directional busing system for conducting vector and scalar data objects between said memory and said buffer, and between said buffer and said functional units, said improvement comprising:

clock means for generating a bus transfer signal including multiple bus transfer cycles, each of said bus transfer cycles including a first and a second transfer phase;

multiple, bi-directional vector memory bus means, each of said vector memory bus means connected to said memory, to said buffer, and to said clock means for conducting a first sequence of vector data elements from said buffer to said memory, each vector data element of said first sequence being conducted during the first phase of each of a first succession of bus transfer cycles, while conducting a second sequence of vector data elements from said memory to said buffer, each of a plurality of vector data elements of said second sequence being conducted during the second phase of each of a plurality of bus transfer cycles in said first succession of bus transfer cycles; and

multiple, bi-directional, function bus means, each of said function bus means connected to said buffer, to said functional units, and to said clock means for conducting a pair of operand scalar data objects or a pair of operand vector data elements from said buffer to said functional units during the first phase of each bus transfer cycle of a second succession of bus transfer cycles, while conducting a result scalar data object or a result vector data element during the second phase of each bus transfer cycle of a plurality of bus transfer cycles in said second succession of bus transfer cycles.

2. A bi-directional data busing system for conducting scalar and vector data objects in a computer which includes a memory for storing vector and scalar data, a plurality of functional units for performing arithmetic and logic operations on vector and scalar operands to produce vector and scalar results, and a buffer with scalar and vector registers for temporarily holding vector and scalar data, said busing system comprising:

a clock unit for generating a bus transfer signal composed of a sequence of bus transfer cycles, each of said bus transfer cycles including a first portion defining a data transfer phase for transferring data from said buffer to said memory or to said functional units, and a second portion defining a result transfer phase for transferring data from said memory or said functional units to said buffer;

multiple bi-directional memory bus means, each connected to said memory, to said buffer, and to said clock unit for conducting a first vector data element from said buffer to said memory during the data phase of each bus transfer cycle of a first sequence of bus transfer cycles, while conducting a second vector data element from said memory to said buffer during the result phase of a bus transfer cycle of said first sequence;

multiple bi-directional function bus means, each connected to said functional units, to said buffer, and to said clock unit for conducting a pair of operand scalar data elements or a pair of operand vector data elements from said buffer to said functional units during the data phase of each bus transfer cycle of a second sequence of bus transfer cycles, while conducting a result scalar data element or a result vector data element from said functional units to said buffer during the result phase of a bus transfer cycle of said second sequence; and

machine control means connected to said memory, to said buffer, to said functional units, and to said clock unit and responsive to a succession of program instructions for selectively connecting a first vector register with a respective memory data bus means to provide said first vector data elements, while selectively connecting a second vector register with said respective memory data bus means to receive said second vector data element, and for selectively connecting first and a second scalar registers or third and fourth vector registers with a respective function bus means to provide said pair of operand scalar elements or said pair of operand vector elements, while selectively connecting a third scalar register or a fifth vector register with said respective function bus means to receive said result scalar data element or said result vector element.

3. The busing system of claim 2 wherein said multiple, bi-directional memory bus means includes a bi-directional scalar memory bus for conducting a scalar data element from said buffer to said memory during the data phase of a respective bus transfer cycle while conducting a scalar element from said memory to said buffer during the result phase of said respective bus transfer cycle.

4. The busing system of claim 2 wherein each of said multiple bi-directional function bus means includes a pair of signal paths, a first of said signal paths being bi-directional, and a second of said signal paths being uni-directional.

5. The busing system of claim 4, wherein said first signal path is for conducting an operand scalar data element or an operand vector data element from said buffer to said functional units during the data phase of a respective bus transfer cycle, and for conducting a result scalar data element or a result vector data element from said functional units to said buffer during the result phase of said respective bus transfer cycle, and said second signal path is for conducting an operand scalar data element or an operand vector data element during said data phase of said respective bus transfer cycle.

6. The busing system of claim 2 wherein each of said bi-directional memory bus means has a memory data element transfer capacity, each of said bi-directional function bus means has an operand data element transfer capacity, and wherein said data element transfer capacity of each of said memory bus means has a predetermined parametric relationship with said operand data element transfer capacity of each of said bi-directional function bus means.

7. The busing system of claim 2 wherein said machine control means includes vector control means for transferring a stream of operand vector data elements from said third or said fourth vector registers to said respective function bus means, while transferring, in synchronism with said stream of operand vector data elements, a stream of result vector data elements to said fifth vector register from said respective function bus means.

8. The busing system of claim 7 wherein said stream of result vector data elements is interruptible and said vector control means includes scheduling means for interruptibly transferring said result vector data element stream in synchronism with interruptions in said stream of operand vector data elements.

9. A method of conducting scalar and vector data in a computer system including a memory for entering vector and scalar data, a plurality of functional units for performing arithmetic and logical operations on vector and scalar operand data to produce vector and scalar result data, a buffer including vector registers and scalar registers, a plurality of bi-directional vector memory buses for conductively connecting said memory with said vector registers, and a plurality of bi-directional function buses for conductively connecting said vector and scalar registers with said functional units, said method comprising the steps of:

generating a bus transfer signal including a string of multi-phase bus transfer cycles, each of said bus transfer cycles including a data phase and a result phase;

identifying a first vector register for temporarily storing a first vector data object, said vector data object including an ordered plurality of vector data elements;

selecting a respective memory bus for conducting said vector data object from said first vector register to said memory;

conducting a first vector data element of said vector data object on said respective memory bus to said memory during the data phase of a first respective bus transfer cycle;

selecting said respective memory bus for conducting a second vector data element from said memory to a second vector register;

conducting said second vector data element on said respective memory bus from said memory during the result phase of said first respective bus transfer cycle; and

conducting a third vector data element of said first vector data object on said respective memory bus to said memory during the data phase of a second bus transfer cycle, said second bus transfer cycle following said first bus transfer cycle in said string.

10. A method of conducting scalar and vector data in a computer system including a memory for entering vector and scalar data, a plurality of functional units for performing arithmetic and logical operations on vector and scalar operand data to produce vector and scalar result data, a buffer, including vector registers and scalar registers, a plurality of bi-directional vector memory buses for conductively connecting said memory with said vector registers, and a plurality of bi-directional function buses for conductively connecting said vector and scalar registers with said functional units, said method comprising the steps of:

generating a bus transfer signal including a string of multi-phase bus transfer cycles, each of said bus transfer cycles including a data phase and a result phase;

identifying a first vector register for temporarily storing a first vector data object, said first vector data object including an ordered plurality of vector data elements;

selecting a respective function bus for conducting said vector data object from said first vector register to said functional units;

conducting a first vector data element of said first vector data object on said respective function bus to said functional units during the data phase of a first respective bus transfer cycle;

selecting said respective function data bus for conducting a second vector data element from said functional units to a second vector register;

conducting said second vector data element from said functional units on said respective function data bus during the result phase of said first respective bus transfer cycle; and

conducting a third vector data element of said vector data object on said respective function bus to said functional units during the data phase of a second respective bus transfer cycle, said second respective bus transfer cycle following said first respective bus transfer cycle in said string.

11. The method of claim 10, further including the steps of:

identifying a third vector register for temporarily storing a second vector data object, said second vector data object including an ordered plurality vector data elements;

selecting a respective memory bus for conducting said second vector data object from said third vector register to said memory;

conducting a first vector data element of said second vector data object on said respective memory bus to said memory during the data phase of a third respective bus transfer cycle;

selecting said respective memory bus for conducting a fourth vector data element from said memory to a fourth vector register;

conducting said fourth vector data element on said respective memory bus from said memory during the result phase of said third respective bus transfer cycle;

conducting a second vector data element of said second vector data object on said respective memory bus to said memory during the data phase of a fourth bus transfer cycle, said fourth bus transfer cycle following said fourth bus transfer cycle in said string.

12. The method of claim 10, further including the steps of:

identifying a scalar register;

selecting said respective function bus for conducting a scalar data element from said functional units to said scalar register;

conducting said scalar data element on said respective functional bus from said functional units during the result phase of said second bus transfer cycle.