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Bi-directional databus system for supporting superposition of vector and scalar operations in a computer

  • US 4,760,518 A
  • Filed: 02/28/1986
  • Issued: 07/26/1988
  • Est. Priority Date: 02/28/1986
  • Status: Expired due to Term
First Claim
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1. In a computer including a memory for storing vector data objects and scalar data objects, said vector data objects each including an ordered array of vector data elements, functional units for performing arithmetic and logical operations on vector and scalar data objects, and a buffer including vector registers for temporary storage of vector data objects and scalar registers for temporary storage of scalar data objects, wherein the improvement is a bi-directional busing system for conducting vector and scalar data objects between said memory and said buffer, and between said buffer and said functional units, said improvement comprising:

  • clock means for generating a bus transfer signal including multiple bus transfer cycles, each of said bus transfer cycles including a first and a second transfer phase;

    multiple, bi-directional vector memory bus means, each of said vector memory bus means connected to said memory, to said buffer, and to said clock means for conducting a first sequence of vector data elements from said buffer to said memory, each vector data element of said first sequence being conducted during the first phase of each of a first succession of bus transfer cycles, while conducting a second sequence of vector data elements from said memory to said buffer, each of a plurality of vector data elements of said second sequence being conducted during the second phase of each of a plurality of bus transfer cycles in said first succession of bus transfer cycles; and

    multiple, bi-directional, function bus means, each of said function bus means connected to said buffer, to said functional units, and to said clock means for conducting a pair of operand scalar data objects or a pair of operand vector data elements from said buffer to said functional units during the first phase of each bus transfer cycle of a second succession of bus transfer cycles, while conducting a result scalar data object or a result vector data element during the second phase of each bus transfer cycle of a plurality of bus transfer cycles in said second succession of bus transfer cycles.

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