Arithmetic logic and shift device

• US 4,760,544 A
• Filed: 06/20/1986
• Issued: 07/26/1988
• Est. Priority Date: 06/20/1986
• Status: Expired due to Term

• Current Assignee: Plessey Semiconductors Limited (Plessey Group Holdings Ltd.)
• Original Assignee: Plessey Overseas Limited (Marconi Holdings Company Limited)
• Inventors: Lamb, Kenneth J.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Mai, Tan V.
• Application Number:
  US06/876,533
• Time in Patent Office: 767 Days
• Field of Search: 364/736, 364/754, 364/752-760, 364/748
• US Class Current: 708/524
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence

Abstract

A device which includes an arithmetic logic unit and a data shifter--e.f. a barrel shifter. The outputs of these are cross-coupled to their inputs by separate feedback connections. A third feedback connection is provided between the output of the arithmetic logic unit and another of its inputs. For added versatility in operation, registers at the output of the arithmetic logic unit and the barrel shifter may include each a selectable by-pass and/or additional registers may be included in parallel therewith. The device is reconfigured by the control of input multiplexers interposed between the feedback connections and the arithmetic logic unit and the barrel shifter.

Claims

1. An arithmetic logic and shift device comprising:

an arithmetic logic unit;

first and second input multiplexers connected to respective inputs of said arithmetic logic unit;

a data shift means;

a third input multiplexer connected to an input of said data shift means;

first and second data input ports connected respectively to an input of the first input multiplexer and to an input of the third input multiplexer;

a first connective feedback path connected to the third input multiplexer to feedback data output from the arithmetic logic unit;

a second and independent connective feedback path connected to the second input multiplexer to feedback data output from the data shift means;

a third and independent connective feedback path connected to the first input multiplexer to feedback only data output from the arithmetic logic unit;

a data output port; and

an output multiplexer, connected at respective inputs to receive data from the arithmetic logic unit and from said data shift mean, and connected at output to the data output port to select and pass data thereto.

2. A device, as claimed in claim 1, wherein the data shift means is a barrel shifter.

3. A device, as claimed in claim 1, wherein an output register is interposed between the arithmetic logic unit and the first and third feedback paths.

4. A device, as claimed in claim 3, wherein the output register is provided with a by-pass.

5. A device, as claimed in claim 3, wherein at least one additional output register is connected in parallel to said output register.

6. A device, as claimed in claim 1, wherein an output register is interposed between the data shift means and the second feedback path.

7. A device, as claimed in claim 6, wherein the output register is provided with a by-pass.

8. A device, as claimed in claim 6, wherein at least one additional output register is connected in parallel to said output register.

9. An arithmetic logic and shift device comprising:

an arithmetic logic unit;

first and second input multiplexers connected to respective inputs of said arithmetic logic unit;

first and second output registers connected in parallel to an output of the arithmetic logic unit;

a barrel shifter;

a third input multiplexer connected to an input of said barrel shifter;

first and second data input ports connected respectively to an input of the first input multiplexer and to an input of the third multiplexer;

third and fourth output registers connected in parallel to an output of the barrel shifter;

a first connective feedback path connected between the third input multiplexer and the first and second output registers;

a second and independent feedback path connected between the second input multiplexer and the third and fourth output registers;

a third and independent feedback path connected between the first input multiplexer and the first and second output registers;

a first data input register connected to the first input multiplexer;

a second data input register connected to the both second and third input multiplexer;

an output connected at respective inputs to the first and second, third and fourth, output registers;

an output port; and

an output enable gate connected between the output port and an output of the output multiplexer.

10. A device, as claimed in claim 9, wherein the second input register is connected to all three first, second, and third, input multiplexers;

and, the third and fourth output registers are connected to both first and second input multiplexers.