Ring network for communication between one chip processors
First Claim
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1. A ring network for communication between one chip processors each having a serial transmitter and a serial receiver comprising:
- a ring line means;
a plurality of network driver means, one for each one chip processor and adapted each to selectively couple said transmitter or said receiver to said ring line means or to pass signals present on said ring line means when the associated one chip processor has no transmission privilege;
control means included in each of said one chip processors for selectively operating said one chip processor as an independent local data processor and selectively as a network controller according to a predetermined priority granting method;
a first and second tristate line driver included in said network driver means and connected to said ring line means;
a timing means for each one chip processor having an input connected to an output of said transmitter of the associated one chip processor and adapted to be triggered by a start bit generated by said transmitter enabling said first tristate line driver to pass serial data from said transmitter to said ring line means and said second tristate line driver to block passing of said signals present on said ring line means.
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Abstract
The present invention relates to a data transmission system having a ring network for communication between one chip processors each having a serial transmitter and serial receiver. Each one chip processor can operate as an independent local processor or as a network controller communicating via a network driver and the ring network with other one chip processors. Transmission privilege is transformed from a first one chip processor having completed transmission to the next processor in sequence which is ready for transmission, thereby reducing unnecessary waiting time.
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Citations
15 Claims
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1. A ring network for communication between one chip processors each having a serial transmitter and a serial receiver comprising:
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a ring line means; a plurality of network driver means, one for each one chip processor and adapted each to selectively couple said transmitter or said receiver to said ring line means or to pass signals present on said ring line means when the associated one chip processor has no transmission privilege; control means included in each of said one chip processors for selectively operating said one chip processor as an independent local data processor and selectively as a network controller according to a predetermined priority granting method; a first and second tristate line driver included in said network driver means and connected to said ring line means; a timing means for each one chip processor having an input connected to an output of said transmitter of the associated one chip processor and adapted to be triggered by a start bit generated by said transmitter enabling said first tristate line driver to pass serial data from said transmitter to said ring line means and said second tristate line driver to block passing of said signals present on said ring line means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of operating a ring network for communication between a plurality of one chip processors comprising the steps of:
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establishing a ring line means; providing a plurality of network driver means, one for each of said one chip processors to selectively couple each one chip processor to said ring line means; operating each said one chip processor as a network controller to communicate with any other one chip processor via said network driver means and said ring line means; operating said network controllers for transferring transmission privilege from a first one chip processor upon completion of transmission to that said one chip processor ready for transmission and being next in electrical sequence to said first one chip processor; and wherein data transmitted by one of said one chip processors are subdivided into blocks individually checked by the receiving one chip processor returning an error signal to said transmitting one chip processor in case of an error in the received data, the transmitting one chip processor retransmitting that block of data only containing the error before continuing transmission.
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Specification