Ring network for communication between one chip processors

• US 4,760,571 A
• Filed: 07/24/1985
• Issued: 07/26/1988
• Est. Priority Date: 07/25/1984
• Status: Expired due to Fees

• Current Assignee: Siegfried Schwarz
• Original Assignee: Siegfried Schwarz
• Inventors: Schwarz, Siegfried
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Scutch, III, Frank M.
• Application Number:
  US06/758,389
• Time in Patent Office: 1,098 Days
• Field of Search: 370/86, 370/88, 370/89, 370/85, 340/825.05, 340/825.5, 340/825.52, 375/36, 371/32, 371/33
• US Class Current: 370/445
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 12/433 with asynchronous transmission, e.g. token ring, register insertion

Abstract

The present invention relates to a data transmission system having a ring network for communication between one chip processors each having a serial transmitter and serial receiver. Each one chip processor can operate as an independent local processor or as a network controller communicating via a network driver and the ring network with other one chip processors. Transmission privilege is transformed from a first one chip processor having completed transmission to the next processor in sequence which is ready for transmission, thereby reducing unnecessary waiting time.

Claims

1. A ring network for communication between one chip processors each having a serial transmitter and a serial receiver comprising:

a ring line means;

a plurality of network driver means, one for each one chip processor and adapted each to selectively couple said transmitter or said receiver to said ring line means or to pass signals present on said ring line means when the associated one chip processor has no transmission privilege;

control means included in each of said one chip processors for selectively operating said one chip processor as an independent local data processor and selectively as a network controller according to a predetermined priority granting method;

a first and second tristate line driver included in said network driver means and connected to said ring line means;

a timing means for each one chip processor having an input connected to an output of said transmitter of the associated one chip processor and adapted to be triggered by a start bit generated by said transmitter enabling said first tristate line driver to pass serial data from said transmitter to said ring line means and said second tristate line driver to block passing of said signals present on said ring line means.

2. The ring network of claim 1 wherein said second tristate line driver passes said signals present on said ring line means when said timing means is inoperative.

3. The ring network of claim 1 further comprising a supply voltage detector means for issuing a blocking signal when detecting an excess supply voltage drop, said signal blocking said first tristate line driver and shunting said network driver means associated thereto for passing said signals present on said ring line means essentially without attenuation.

4. The ring network of claim 1 wherein said network driver means include an amplifier having inputs connected in series to said ring line means and an output connected to said receiver and to an input of a noise removing means having its output connected to an input of said second tristate line driver an output of which is connected in series to said ring line means.

5. The ring network of claim 4 wherein said noise removing means comprise the series connection of a resistor and an amplifier the latter being shunted by a capacitor.

6. The ring network of claim 1, wherein said timing means is a monoflop.

7. The ring network of claim 3, wherein said network driver means is shunted via switching means operable by said blocking signal generated by said supply voltage detector means.

8. The ring network of claim 7, wherein said switching means are FET-Transistors.

9. The ring network of claim 1, wherein said priority granting method is a CSMA/CD method.

10. The ring network of claim 1, wherein said priority granting method is a token passing method.

11. The ring network of claim 1, wherein said priority granting method is a combination of the CSMA/CD and the token passing methods.

12. The ring network of claim 1, wherein said control means of an associated one chip processor causes the latter upon completion of the data transmission to transfer its transmission privilege to that of said one chip processors ready for transmission and being next in electrical sequence to said first one chip processor.

13. The ring network of claim 12, wherein for a transfer of said transmission privilege from a one chip processor the latter first transmits an announcement received by all one chip processors whilst the information following the announcement is received by the next following one chip processor only ready for transmission request and which blocks the further transfer of said information to any others of said one chip processors.

14. The ring network of claim 13, wherein upon receipt of said information by said next following one chip processor a transmission request flag is reset whilst a transmission privilege flag is set.

15. A method of operating a ring network for communication between a plurality of one chip processors comprising the steps of:

establishing a ring line means;

providing a plurality of network driver means, one for each of said one chip processors to selectively couple each one chip processor to said ring line means;

operating each said one chip processor as a network controller to communicate with any other one chip processor via said network driver means and said ring line means;

operating said network controllers for transferring transmission privilege from a first one chip processor upon completion of transmission to that said one chip processor ready for transmission and being next in electrical sequence to said first one chip processor;

and wherein data transmitted by one of said one chip processors are subdivided into blocks individually checked by the receiving one chip processor returning an error signal to said transmitting one chip processor in case of an error in the received data, the transmitting one chip processor retransmitting that block of data only containing the error before continuing transmission.