Apparatus and method for implementing transformations in grayscale image processing

• US 4,760,607 A
• Filed: 07/31/1986
• Issued: 07/26/1988
• Est. Priority Date: 07/31/1986
• Status: Expired due to Fees

• Current Assignee: Machine Vision International Corporation
• Original Assignee: Machine Vision International Corporation
• Inventors: Herteg, Glenn, Koskella, Martin P., Sternberg, Stanley R., Rau, Robert S.
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US06/891,311
• Time in Patent Office: 726 Days
• Field of Search: 382/49, 382/41, 382/27, 358/283
• US Class Current: 382/307
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

The specification discloses a system and method for processing serialized digital representations of grayscale images. The system includes a geometric logic unit through which the serialized representations are passed. The geometric logic unit includes an arithmetic logic unit (ALU) and an ALU controller which operate on the serialized signal and a delayed version thereof on a word-by-word basis. The function unit is capable of performing a dynamically selectable function and appropriately clips the resultant data to maintain the data within range.

Claims

1. An image processor for processing a digital signal representative of a grayscale image made up of a matrix of points, the digital signal being a plurality of serial multibit words each corresponding to one of the image points, said processor including a logic unit through which the digital signal is passed, said logic unit comprising:

input port means for receiving the digital signal;

delay means for delaying the digital signal to produce a delayed signal;

memory means for storing a dynamically selectable constant enhancement value and a dynamically selectabel constant limit value;

control means for dynamically selecting the enhancement value and the limit value;

an arithmetic logic unit (ALU) means including means for adding or subtracting the constant enhancement value to each word in the delayed signal to produce an enhanced signal, said ALU means further including a first status flag indicative of whether overflow occurred as a result of said addition or subtraction, said ALU means further including means for subtracting each word of one of the enhanced and digital signals from each corresponding word of the other of the enhanced and digital signals, said ALU means further including a second status flag indicative of whether overflow occurred as a result of said subtraction; and

output means for outputting an output signal, said output means including selector means responsive to the first and second status flags for selecting each word of the output signal from one of the constant limit value, the corresponding word from the digital signal, and the corresopnding word from the enhanced signal.

2. An image processor as defined in claim 1 wherein each of said first and second status flags comprises a binary signal and further wherein said output selector means comprises a multiplexer driven by a select signal including said first and second status flags.

3. An image processor as defined in claim 2 wherein said multiplexer outputs the limit value when said first status flag is set.

4. An image processor as defined in claim 3 wherein said multiplexer outputs one of the input signal word and the enhanced signal word when the first status flag is not set.

5. An image processor as defined in claim 1 wherein the limit value is the largest number representable in one of the multibit words.

6. An image processor as defined in claim 1 wherein the limit value is zero.

7. An image processor as defined in claim 1 wherein said ALU means comprises a single arithmetic logic unit digital device.

8. A method of processing a digital signal representative of a grayscale image made up of a matrix of points, the digital signal being a plurality of serial multibit words each corresponding to one of the image points, said method comprising:

receiving the digital signal;

delaying the digital signal to produce a dealyed signal;

dynamically selecting a constant enhancement value and a constant limit value;

adding or subtracting the constant enhancement value to each word in the delayed signal to produce an enhanced signal noting whether overflow occurs;

subtracting each word in one of the enhanced and digital signals from the corresponding word in the other of the enhanced and digital signals noting whether overflow occurs;

selecting the constant limit value, the enhanced signal word, or the digital signal word depending on whether overflow occurred on either or both of the preceding steps; and

outputting the selected values as a serial output signal.

9. A method as defined in claim 8 wherein said selecting step comprises multiplexing the limit value, the enhanced signal words, and the digital signal words using overflow status flags generated by said adding and subtracting steps as a select signal.

10. A method as defined in claim 9 wherein said multiplexing step comprises selecting the limit value when overflow occured on said first adding or subtracting step.

11. A method as defined in claim 10 wherein said multiplexing step comprises selecting one of the digital signal word and the enhanced signal word when overflow did not occur on said first adding or subtracting step.

12. A method as defined in claim 8 wherein the limit value is the maximum number representable in one of the multibit words.

13. A method as defined in claim 8 wherein the limit value is zero.