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Clock scheme for VLSI systems

  • US 4,761,567 A
  • Filed: 05/20/1987
  • Issued: 08/02/1988
  • Est. Priority Date: 05/20/1987
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising:

  • an input pad connected to receive a first external clock signal;

    input clock generator means responsive to said first clock signal for generating an internal system clock signal;

    means for selectively enabling or disabling of said input clock generator means;

    input/output pad connected to receive said internal system clock signal and to provide said internal system clock signal to other integrated circuits;

    internal clock generator means being responsive to said internal system clock signal for generating a first internal phase clock signal and a second internal phase clock signal which is complementary to the first internal phase clock signal when said input clock generator means is enabled;

    said input/output pad being further connected to receive a second external system clock signal when said input clock generator means is disabled; and

    said internal clock generator means being responsive to said second external system clock signal for generating said first and second internal phase clock signals when said input clock generator means is disabled.

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