Clock scheme for VLSI systems
First Claim
Patent Images
1. An integrated circuit comprising:
- an input pad connected to receive a first external clock signal;
input clock generator means responsive to said first clock signal for generating an internal system clock signal;
means for selectively enabling or disabling of said input clock generator means;
input/output pad connected to receive said internal system clock signal and to provide said internal system clock signal to other integrated circuits;
internal clock generator means being responsive to said internal system clock signal for generating a first internal phase clock signal and a second internal phase clock signal which is complementary to the first internal phase clock signal when said input clock generator means is enabled;
said input/output pad being further connected to receive a second external system clock signal when said input clock generator means is disabled; and
said internal clock generator means being responsive to said second external system clock signal for generating said first and second internal phase clock signals when said input clock generator means is disabled.
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Abstract
An integrated circuit includes an input clock generator circuit responsive to an external TTL level clock signal for generating an internal CMOS level system clock signal for its own use and for use by other integrated circuits. The integrated circuit also includes an internal clock generator circuit responsive to either the internal CMOS level system clock signal or an external CMOS level system clock signal for generating internal CMOS level phase clock signals for its own use. As a result, the integrated circuit has a higher speed of operation since the propagation delay between the CMOS level system clock signal and internal clock signals has been minimized.
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Citations
12 Claims
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1. An integrated circuit comprising:
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an input pad connected to receive a first external clock signal; input clock generator means responsive to said first clock signal for generating an internal system clock signal; means for selectively enabling or disabling of said input clock generator means; input/output pad connected to receive said internal system clock signal and to provide said internal system clock signal to other integrated circuits; internal clock generator means being responsive to said internal system clock signal for generating a first internal phase clock signal and a second internal phase clock signal which is complementary to the first internal phase clock signal when said input clock generator means is enabled; said input/output pad being further connected to receive a second external system clock signal when said input clock generator means is disabled; and said internal clock generator means being responsive to said second external system clock signal for generating said first and second internal phase clock signals when said input clock generator means is disabled. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit comprising:
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an input pad connected to receive an external TTL level clock signal; input clock generator means responsive to said TTL level clock signal for generating an internal CMOS level system clock signal; means for selectively enabling or disabling of said input clock generator means; input/output pad connected to receive said internal CMOS level system clock signal and to provide said internal system clock signal to other integrated circuits; internal clock generator means being responsive to said internal CMOS level system clock signal for generating a first internal CMOS level phase clock signal and a second internal CMOS level phase clock signal which is complementary to the first internal CMOS level phase clock signal when said input clock generator means is enabled; said input/output pad being further connected to receive a common external CMOS level system clock signal when said input clock generator means is disabled; and said internal clock generator means being responsive to said common external CMOS level system clock signal for generating said first and second internal CMOS level phase clock signals when said input clock generator means is disabled. - View Dependent Claims (11, 12)
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Specification