Programmable logic device

• US 4,761,768 A
• Filed: 03/04/1985
• Issued: 08/02/1988
• Est. Priority Date: 03/04/1985
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Rutledge, David L., Turner, John E.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US06/707,662
• Time in Patent Office: 1,247 Days
• Field of Search: 371/21, 371/25, 365/185, 365/201, 340/825.87, 340/825.79, 340/825.8, 340/825.83, 340/825.89, 340/825.90, 307/465, 307/468, 357/23.5, 364/716
• US Class Current: 365/185.22
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17764 for reliability
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

An improved programmable logic device (PLD) is disclosed which employs electrically erasable memory cells which can be programmed and erased at high speed. The PLD memory cells comprise floating gate transistors as the storage elements, which are programmed and erased by Fowler-Nordheim tunneling. The PLD includes a serial register latch (SRL) which is coupled to the product terms of the PLD array. Input programming data for a selected row of the array is serially entered into the SRL, and during a programming cycle the SRL data is employed to simultaneously program the storage elements of the selected row to either the enhancement mode or the depletion mode. The data programmed into the array may be verified at high speed. The status of each of the cells in the selected row can be sensed using the normal sense amplifiers and loaded into the SRL in parallel, and thereafter serially shifted out of the PLD for external verification. The PLD output logic and sense amplifiers can be functionally validated independent of the data in the array. Test data such as apparent array patterns are serially loaded into the SRL, and thereafter forced onto the normal sense amplifier inputs, propagated through the output logic and read out of the device output pin.

Claims

1. In an integrated programmable logic device comprising a plurality of input lines, a plurality of product terms, a matrix of programmable cells each selectively coupling respective ones of said input lines to respective ones of said product terms, and output logic circuits coupling said product terms to device terminals, the improvement wherein:

said programmable cells each comprise an electrically erasable and reprogrammable floating gate transistor having a source and a drain and employing Fowler-Nordheim tunneling to achieve charge transfer between the floating gate and the transistor drain so that the transistor may be operated in either the enhancement mode or the depletion mode, whereby the transistor is either conductive or nonconductive when an interrogation signal is applied to the gate of the floating gate transistor, and a cell select transistor connected in series relation with said floating gate transistor and whose state is controlled by a respective input line signal;

said device further comprises means for programming the floating gate transistors comprising said cells to either the enhancement mode or the depletion mode, said programming means adapted to program in parallel the cells coupled to a selected input line whose cell select transistors have been gated to the conductive state; and

cell verification means for reading in parallel the programmed states of the respective cells coupled to a selected input line and providing a data sequence representative of respective programmed states at a device output port.

2. The improvement of claim 1 wherein said output logic circuits coupling said product terms to device terminals comprises means for performing a logical OR function on selected product term logical states.

3. An improved integrated programmable logic device, comprising:

a plurality of input lines coupled to device input ports;

a matrix of reprogrammable cells, each cell selectively coupling a particular input line to a respective product term;

a plurality of sense amplifiers, one each coupled to a respective product term for providing a sense amplifier logical state dependent on the logical states of those input lines selectively coupled to said respective product term;

output logic circuitry responsive to said respective sense amplifier logical states for providing device logical output signals at one or more device output terminals;

programming means for parallel programming in a single programming cycle the respective cells coupled to a selected input line in accordance with a predetermined programming data pattern; and

cell verification means for reading in parallel the programmed states of the respective cells coupled to a selected input line and providing a data sequence representative of the respective programmed states at a device terminal.

4. The programmable logic device of claim 3 wherein said programming means includes (i) a serial shift register latch (SRL) comprising a plurality of series-connected stages, (ii) means for selectively coupling respective stages of said SRL to each cell associated with a corresponding product term, and (iii) means for serially entering data representative of said programming data pattern into said SRL via a serial input data port of the device.

5. The programmable logic device of claim 4 further comprising a serial data output port, and wherein the verification means comprises said SRL, means for coupling each of said stages to a corresponding one of said sense amplifiers, means for loading data representative of the state of respective cells of a selected row of said matrix into corresponding stages of said SRL, and means for thereafter serially shifting the contents of said SRL out of the serial data port of said device.

6. The programmable logic device of claim 4 further comprising output logic verification means for verifying the operation of said output logic, comprising means for inputting an apparent row pattern into said SRL, means for selectively coupling the respective stages of the SRL to the respective sense amplifiers to drive the respective sense amplifiers with said apparent row pattern, whereby the resulting device output bit pattern may be compared against an expected bit pattern.

7. An improved integrated programmable logic device, comprising:

a plurality of input lines;

a plurality of product term lines;

an array of nonvolatile electrically erasable and programmable switch elements, each coupled to a predetermined one of said input lines and said product term lines, and arranged to selectively couple said input line to said product term, or to isolate said input line from said product term, in dependence on the state of said switch element;

a plurality of sensing means, one each coupled to a respective one of said product terms, for sensing the logical state of said product term and providing a logical sense signal indicative of said logical state;

output logic circuitry responsive to said respective logical sense signals for providing device output signal at one or more device terminals; and

verification means for verifying the operation of said sensing means and said output logic circuitry, said verification means comprising means for forcing an arbitrary, used-applied apparent array logical data pattern onto the respective inputs of said sensing means for each product term through selected conductive cells of said array, and means for propagating said apparent array pattern through said sensing means and said output logic circuitry in dependence on their operational state.

8. The invention of claim 7 wherein said verification means comprises:

serial shift register means comprising a plurality of serially-connected stages, each selectively coupled to the input of corresponding ones of said sensing means in response to control signals; and

means for loading said apparent array data pattern into the stages of said shift register means and thereafter coupling the data contents of the respective stages of the shift register means to the inputs of the corresponding sensing means for forcing the data content of the respective stage onto the respective inputs of the sensing means.

9. An integrated programmable logic device comprising:

a plurality of input lines;

a plurality of product terms;

output logic circuits coupling said product terms to device terminals;

a matrix of programmable cells each selectively coupling respective ones of said input lines to respective ones of said product terms, said cells comprising;

(i) an electrically erasable floating gate transistor having a source and a drain, and employing Fowler-Nordheim tunneling to achieve charge transfer between the floating gate and the transistor drain so that the transistor may be operated in either the enhancement mode or the depletion mode, whereby the transistor is either conductive or nonconductive when an interrogation signal is applied to the gate; and

(ii) a cell select transistor connected in series relation with said floating gate transistor and whose state is controlled by a respective input line signal; and

means for programming the floating gate transistors to either the enhancement mode or the depletion mode, said means adapted to program in parallel each of the cells coupled to a selected input line and comprising;

(i) a serial shift register means comprising a plurality of serially-connected stages coupled to corresponding product terms,

(ii) means for selectively coupling respective stages of said shift register means to each selected cell associated with a corresponding product term,

(iii) means for loading the stages of said shift register means with data corresponding to the state to which the cell is to be programmed, and

(iv) means for applying programming voltages to said floating gate transistors comprising said cells coupled to said selected input line in dependence on the state of said data in the respective stages of the shift register means.

10. The integrated programmable logic device of claim 9 wherein said output logic circuits comprise means for performing a logical OR function on the logical states of selected ones of the product terms.

11. An integrated programmable logic device comprising:

a plurality of input lines;

a plurality of product terms;

output logic circuits coupling said product terms to device terminals;

a matrix of programmable cells each selectively coupling respective ones of said input lines to respective ones of said product terms, said cells comprising;

(i) an electrically erasable floating gate transistor having a source and a drain and employing Fowler-Nordheim tunneling to achieve charge transfer between the floating gate and the transistor drain so that the transistor is either conductive or nonconductive when an interrogation signal is applied to the gate; and

(ii) a cell select transistor connected in series relation with said floating gate transistor and whose state is controlled by a respective input line signal; and

means for programming the floating gate transistors to either the conductive-when-interrogated state or the nonconductive-when-interrogated state, said means adapted to program in parallel each of the cells coupled to a selected input line and comprising;

(i) a serial shift register means comprising a plurality of serially-connected stages,

(ii) means for selectively coupling respective stages of said shift register means to each cell associated with a corresponding product term,

(iii) means for loading the stages of said shift register means with data corresponding to the state to which the cell is to be programmed, and

(iv) means for applying programming voltages to said floating gate transistors comprising said cells coupled to said selected input line in dependence on the state of said data in the respective stages of the shift register means.

12. The programmable logic device of claim 11 wherein said programming means comprises bulk erasing means for simultaneously programming each of the floating gate transistors comprising the cells to the enhancement mode.

13. The programmable logic device of claim 12 wherein said bulk erasing means comprises means for applying high programming potential to the gates of said floating gate transistor means, means for driving each of said select transistors to the conductive state, and means for grounding the respective drains of said floating gate transistors during a bulk erase cycle.

14. The integrated programmable logic device of claim 11 wherein said output logic circuits comprise means for performing a logical OR function on the logical states of selected ones of the product terms.

15. An integrated semiconductor programmable logic device comprising:

a plurality of input lines coupled to device input terminals;

a plurality of product terms;

a plurality of sensing means, one each coupled to a respective product term for sensing the logical state of said product term and providing a sense signal indicative of said logical state;

a plurality of output logic circuits responsive to said sense signals for providing device output signals at one or more device output terminals;

a plurality of electrically erasable and reprogrammable cells, each for selectively coupling respective ones of said input lines to respective ones of said product terms when the cell is in a conductive state and for isolating said input line from said product term when the cell is in a non-conductive state;

means for verifying the respective state of selected ones of said cells, said means comprising;

means for operatively selecting one of the cells coupled to each product term such that the logical state of said product term is dependent upon the state of said selected cell;

said sensing means; and

means coupled to said sensing means for substantially simultaneously reading said sense signals and thereafter providing serial data representative of the states of the selected cells at a device external port.

16. The invention of claim 15 wherein said plurality of reprogrammable cells are arranged in a matrix of rows and columns, each of the respective cells in a given row is coupled to a corresponding input line, and each of the respective cells in a given column is coupled to a corresponding product term, and wherein said means for operatively selecting one of the cells coupled to each product term selects all cells disposed in a selected row.

17. The invention of claim 16 wherein said cells of said matrix each comprise first and second transistor means, said first transistor means adapted to select the cell for programming in dependence upon row address selection signals, and said second transistor is a floating gate transistor adapted to connect said input line to the corresponding product term when programmed to the conductive state, and to isolate said input line from the corresponding product term when programmed to the nonconductive state.

18. An integrated programmable logic device comprising:

a plurality of input lines;

a plurality of product terms;

a plurality of programmable cells each selectively coupling respective ones of said input lines to respective ones of said product terms in dependence on the programmed state of the respective cell and the logical state of the respective input line, said programmable cells each comprising;

(i) an electrically erasable and reprogrammable floating gate transistor having a source and a drain and employing Fowler-Nordheim tunneling to achieve charge transfer between the floating gate and the transistor drain so that the transistor is either conductive or nonconductive when an interrogation signal is applied to the gate of the transistor; and

(ii) a cell select transistor connected in series relation with said floating gate transistor and whose state is controlled by a respective input line signal;

output logic circuits coupling said product terms to device output terminals to provide device output logical signals whose logical states depend on the logical states of the input lines, the programmed states of said cells and said output logic circuitry, and wherein said output logic circuits comprise means for performing a logical OR function on the logical states of selected ones of the product terms; and

verification means for verifying the operation of said sensing means and said output logic circuitry.

19. An integrated semiconductor programmable logic device comprising:

a plurality of input lines coupled to device input terminals;

a plurality of product terms;

a plurality of output logic circuits coupling said respective product terms to device output terminals;

a plurality of electrically erasable and reprogrammable cells, each for selectively coupling respective ones of said input lines to respective ones of said product terms when the cell is in a conductive state and for isolating said input line from said product term when the cell is in a non-conductive state, said plurality of reprogrammable cells being arranged in a matrix of rows and columns with each of the respective cells in a given row coupled to a corresponding input line, and with each of the respective cells in a given column coupled to a corresponding product term;

means for verifying the respective state of selected ones of said cells, said means comprising;

means for operatively selecting all cells disposed in a selected row whose states are to be verified;

sensing means operatively coupled to said product terms for simultaneously sensing the state of the selected cell associated with each particular product term; and

means selectively coupled to said sensing means for selectively reading said sensed states and thereafter providing data representative of the state of the selected cells at a

device external port, said means comprising;

a serial shift register comprising a plurality of serially-connected stages;

means for loading the respective stages of said shift register with data indicative of the sensed status of said respective selected cells; and

means for shifting said data out of said shift register at an external device terminal.

20. An integrated semiconductor programmable logic device comprising:

a plurality of input lines coupled to device input terminals;

a plurality of product terms;

a plurality of output logic circuits coupling said respective product terms to device output terminals;

a plurality of electrically erasable and reprogrammable cells, each for selectively coupling respective ones of said input lines to respective ones of said product terms when the cell is in an conductive state and for isolating said input line from said product term when the cell is in a nonconductive state, said plurality of programmable cells being arranged in a matrix of rows and columns, with each of the respective cells in a given row coupled to a corresponding input line, and with each of the respective cells in a given column coupled to a corresponding product term;

means for verifying the respective state of selected ones of said cells, said means comprising;

means for operatively selecting all cells disposed in a selected row whose states are to be verified;

sensing means operatively coupled to said product terms for simultaneously sensing the state of the selected cell associated with each particular product term, said sensing means comprising a plurality of sense amplifiers, one each coupled to a respective product term for providing a sense amplifier logical state dependent on the logical states of those input lines selectively coupled to the respective product terms;

said selecting means operating so that the respective sense amplifier logical states are indicative of the states of one respective selected cell coupled to the respective product term; and

means selectively coupled to said sensing means for selectively reading said sensed states and thereafter providing data representative of the state of the selected cells at a device external port;

said means comprising;

a serial shift register latch (SRL) comprising a plurality of series-connected stages;

means for selectively coupling each stage of said SRL to the output of a corresponding sense amplifier for selectively loading the respective amplifier logical state into said register;

a serial data output terminal of said device coupled to the last stage of said SRL; and

means for sequentially propagating the respective logical states loaded into the respective stages of said SRL through the SRL stages to said serial data output port.

21. The programmable logic device of claim 20 wherein said means for selectively coupling each stage of said SRL comprises a transistor switch gates by a verification signal.

22. The programmable logic device of claim 20 further comprising means for programming the respective cells coupled to each input line in accordance with a predetermined data pattern representing the desired conductive/nonconductive state of the respective cells, comprising:

a device serial data input port, a first register of said SRL being coupled to said input port;

means for serially propagating data representative of said predetermined data pattern into said SRL to load the registers of said SRL with said data pattern;

means for selectively coupling each stage of said SRL to each cell associated with a respective product term; and

cell programming means for selectively programming the cells associated with the selected row and the respective product terms in dependence on the state of said programming data.

23. The programmable logic device of claim 22 wherein said programming means further comprises means for programming each of said programmable cells in said matrix to the nonconductive-when-interrogated state during a bulk erasing cycle, and wherein said cell programming means is adapted to program selected ones of the cells in the selected row to the conductive-when-interrogated state.

24. An improved integrated programmable logic device, comprising:

a plurality of input lines coupled to device input ports;

a matrix of programmable cells, each cell selectively coupling a particular input line to a respective product term;

a plurality of sense amplifiers, one each coupled to a respective product term for providing a sense amplifier logical state dependent on the logical states of those input lines selectively coupled to said respective product term;

output logic circuitry responsive to said respective sense amplifier logical states for providing device logical output signals at one or more device output terminals, said circuitry comprising means for performing a logical OR function on selected ones of said respective sense amplifier logical states;

programming means for parallel programming the respective cells coupled to a selected input line in accordance with a predetermined programming data pattern; and

cell verification means for reading in parallel the programmed states of the respective cells coupled to a selected input line and providing a data sequence representative of respective programmed states at a device terminal.

25. An improved integrated programmable logic device, comprising:

a plurality of input lines;

a plurality of product term lines;

an array of nonvolatile electrically erasable and programmable switch elements, each coupled to a predetermined one of said input lines and said product term lines, and arranged to selectively couple said input line to said product term, or to isolate said input line from said product term, in dependence on the state of said switch element;

a plurality of sensing means, one each coupled to a respective one of said product terms, for sensing the logical state of said product term and providing a logical sense signal indicative of said logical state;

output logic circuitry responsive to said respective logical sense signals for providing device logic output signals at one or more device terminals, said circuitry comprising means for performing a logical OR function on selected ones of said respective sense amplifier logical signals; and

verification means for verifying the operation of said sensing means and said output logic circuitry.